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From: Peter Maydell <peter.maydell@linaro.org>
To: qemu-devel@nongnu.org
Subject: [Qemu-devel] [PULL 06/16] arm_gic: Do not force PPIs to edge-triggered mode
Date: Fri, 29 Aug 2014 15:37:18 +0100	[thread overview]
Message-ID: <1409323049-19255-7-git-send-email-peter.maydell@linaro.org> (raw)
In-Reply-To: <1409323049-19255-1-git-send-email-peter.maydell@linaro.org>

From: Adam Lackorzynski <adam@os.inf.tu-dresden.de>

Only SGIs must be WI, done by forcing them to their default
(edge-triggered).

Acked-by: Christoffer Dall <christoffer.dall@linaro.org>
Signed-off-by: Adam Lackorzynski <adam@os.inf.tu-dresden.de>
Message-id: 1408372255-12358-4-git-send-email-adam@os.inf.tu-dresden.de
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 hw/intc/arm_gic.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/hw/intc/arm_gic.c b/hw/intc/arm_gic.c
index e546647..55019c9 100644
--- a/hw/intc/arm_gic.c
+++ b/hw/intc/arm_gic.c
@@ -558,7 +558,7 @@ static void gic_dist_writeb(void *opaque, hwaddr offset,
         irq = (offset - 0xc00) * 4 + GIC_BASE_IRQ;
         if (irq >= s->num_irq)
             goto bad_reg;
-        if (irq < GIC_INTERNAL)
+        if (irq < GIC_NR_SGIS)
             value |= 0xaa;
         for (i = 0; i < 4; i++) {
             if (s->revision == REV_11MPCORE || s->revision == REV_NVIC) {
-- 
1.9.1

  parent reply	other threads:[~2014-08-29 14:37 UTC|newest]

Thread overview: 18+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2014-08-29 14:37 [Qemu-devel] [PULL 00/16] target-arm queue Peter Maydell
2014-08-29 14:37 ` [Qemu-devel] [PULL 01/16] disas/libvixl: Update to upstream VIXL 1.5 Peter Maydell
2014-08-29 14:37 ` [Qemu-devel] [PULL 02/16] target-arm: Fix regression that disabled VFP for ARMv5 CPUs Peter Maydell
2014-08-29 14:37 ` [Qemu-devel] [PULL 03/16] target-arm: Correct Cortex-A57 ISAR5 and AA64ISAR0 ID register values Peter Maydell
2014-08-29 14:37 ` [Qemu-devel] [PULL 04/16] arm_gic: Fix read of GICD_ICFGR Peter Maydell
2014-08-29 14:37 ` [Qemu-devel] [PULL 05/16] arm_gic: GICD_ICFGR: Write model only for pre v1 GICs Peter Maydell
2014-08-29 14:37 ` Peter Maydell [this message]
2014-08-29 14:37 ` [Qemu-devel] [PULL 07/16] arm_gic: Use GIC_NR_SGIS constant Peter Maydell
2014-08-29 14:37 ` [Qemu-devel] [PULL 08/16] aarch64: raise max_cpus to 8 Peter Maydell
2014-08-29 14:37 ` [Qemu-devel] [PULL 09/16] hw/intc/arm_gic: honor target mask in gic_update() Peter Maydell
2014-08-29 14:37 ` [Qemu-devel] [PULL 10/16] target-arm: Make the ARM PMCCNTR register 64-bit Peter Maydell
2014-08-29 14:37 ` [Qemu-devel] [PULL 11/16] arm: Implement PMCCNTR 32b read-modify-write Peter Maydell
2014-08-29 14:37 ` [Qemu-devel] [PULL 12/16] target-arm: Implement PMCCNTR_EL0 and related registers Peter Maydell
2014-08-29 14:37 ` [Qemu-devel] [PULL 13/16] target-arm: Add arm_ccnt_enabled function Peter Maydell
2014-08-29 14:37 ` [Qemu-devel] [PULL 14/16] target-arm: Implement pmccntr_sync function Peter Maydell
2014-08-29 14:37 ` [Qemu-devel] [PULL 15/16] target-arm: Remove old code and replace with new functions Peter Maydell
2014-08-29 14:37 ` [Qemu-devel] [PULL 16/16] target-arm: Implement pmccfiltr_write function Peter Maydell
2014-08-29 15:46 ` [Qemu-devel] [PULL 00/16] target-arm queue Peter Maydell

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