From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:37524) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1XOWQv-00027V-Ii for qemu-devel@nongnu.org; Mon, 01 Sep 2014 14:34:33 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1XOWQo-0003fE-27 for qemu-devel@nongnu.org; Mon, 01 Sep 2014 14:34:29 -0400 Received: from out1-smtp.messagingengine.com ([66.111.4.25]:42020) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1XOWQn-0003dg-VO for qemu-devel@nongnu.org; Mon, 01 Sep 2014 14:34:22 -0400 Received: from compute5.internal (compute5.nyi.internal [10.202.2.45]) by gateway2.nyi.internal (Postfix) with ESMTP id 79662205D3 for ; Mon, 1 Sep 2014 14:34:19 -0400 (EDT) Message-Id: <1409596459.2228712.162374913.35CEF62E@webmail.messagingengine.com> From: David Hoover MIME-Version: 1.0 Content-Transfer-Encoding: 7bit Content-Type: text/plain Date: Mon, 01 Sep 2014 20:34:19 +0200 Subject: [Qemu-devel] ARM Cortex-M IRQs can not be globally disabled List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org Hi, It seems that interrupts are not disabled by CPSIE instruction. The current code apparently ignores (daif&PSTATE_I) for Cortex-M. The patch below is basically identical to the patch that was attached to the following message: https://lists.gnu.org/archive/html/qemu-devel/2011-06/msg00513.html Cheers, David From: David Hoover Date: Mon, 1 Sep 2014 14:24:56 +0200 Subject: [PATCH] ARM Cortex-M IRQs can not be globally disabled Signed-off-by: David Hoover --- cpu-exec.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/cpu-exec.c b/cpu-exec.c index c6aad74..fdebe2b 100644 --- a/cpu-exec.c +++ b/cpu-exec.c @@ -610,8 +610,8 @@ int cpu_exec(CPUArchState *env) We avoid this by disabling interrupts when pc contains a magic address. */ if (interrupt_request & CPU_INTERRUPT_HARD - && ((IS_M(env) && env->regs[15] < 0xfffffff0) - || !(env->daif & PSTATE_I))) { + && !(env->daif & PSTATE_I) + && (!IS_M(env) || env->regs[15] < 0xfffffff0)) { cpu->exception_index = EXCP_IRQ; cc->do_interrupt(cpu); next_tb = 0; -- 1.8.5.2