From: Ard Biesheuvel <ard.biesheuvel@linaro.org>
To: peter.maydell@linaro.org, christoffer.dall@linaro.org,
qemu-devel@nongnu.org
Cc: Rob Herring <rob.herring@linaro.org>,
Ard Biesheuvel <ard.biesheuvel@linaro.org>
Subject: [Qemu-devel] [PATCH v3 2/6] target-arm: do not set do_interrupt handler for AArch64 user mode
Date: Fri, 5 Sep 2014 14:24:53 +0200 [thread overview]
Message-ID: <1409919897-360-3-git-send-email-ard.biesheuvel@linaro.org> (raw)
In-Reply-To: <1409919897-360-1-git-send-email-ard.biesheuvel@linaro.org>
From: Rob Herring <rob.herring@linaro.org>
User mode emulation should never get interrupts and thus should not
use the system emulation exception handler function. Remove the reference,
and '#ifndef USER_MODE_ONLY' the function itself as well, so that we can add
system mode only functionality to it.
Signed-off-by: Rob Herring <rob.herring@linaro.org>
Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
---
target-arm/cpu64.c | 2 ++
target-arm/helper-a64.c | 3 +++
2 files changed, 5 insertions(+)
diff --git a/target-arm/cpu64.c b/target-arm/cpu64.c
index aa42803959be..9f88b9f4eea0 100644
--- a/target-arm/cpu64.c
+++ b/target-arm/cpu64.c
@@ -196,7 +196,9 @@ static void aarch64_cpu_class_init(ObjectClass *oc, void *data)
{
CPUClass *cc = CPU_CLASS(oc);
+#if !defined(CONFIG_USER_ONLY)
cc->do_interrupt = aarch64_cpu_do_interrupt;
+#endif
cc->set_pc = aarch64_cpu_set_pc;
cc->gdb_read_register = aarch64_cpu_gdb_read_register;
cc->gdb_write_register = aarch64_cpu_gdb_write_register;
diff --git a/target-arm/helper-a64.c b/target-arm/helper-a64.c
index 2e9ef64786ae..89b913ee9396 100644
--- a/target-arm/helper-a64.c
+++ b/target-arm/helper-a64.c
@@ -438,6 +438,8 @@ uint64_t HELPER(crc32c_64)(uint64_t acc, uint64_t val, uint32_t bytes)
return crc32c(acc, buf, bytes) ^ 0xffffffff;
}
+#if !defined(CONFIG_USER_ONLY)
+
/* Handle a CPU exception. */
void aarch64_cpu_do_interrupt(CPUState *cs)
{
@@ -512,3 +514,4 @@ void aarch64_cpu_do_interrupt(CPUState *cs)
env->pc = addr;
cs->interrupt_request |= CPU_INTERRUPT_EXITTB;
}
+#endif
--
1.8.3.2
next prev parent reply other threads:[~2014-09-05 12:25 UTC|newest]
Thread overview: 25+ messages / expand[flat|nested] mbox.gz Atom feed top
2014-09-05 12:24 [Qemu-devel] [PATCH v3 0/6] ARM: add PSCI 0.2 support in TCG mode Ard Biesheuvel
2014-09-05 12:24 ` [Qemu-devel] [PATCH v3 1/6] target-arm: add powered off cpu state Ard Biesheuvel
2014-09-09 15:23 ` Peter Maydell
2014-09-05 12:24 ` Ard Biesheuvel [this message]
2014-09-09 15:25 ` [Qemu-devel] [PATCH v3 2/6] target-arm: do not set do_interrupt handler for AArch64 user mode Peter Maydell
2014-09-09 15:27 ` Ard Biesheuvel
2014-09-09 15:42 ` Peter Maydell
2014-09-05 12:24 ` [Qemu-devel] [PATCH v3 3/6] target-arm: add hvc and smc exception emulation handling infrastructure Ard Biesheuvel
2014-09-09 17:45 ` Peter Maydell
2014-09-09 21:51 ` Ard Biesheuvel
2014-09-09 21:59 ` Peter Maydell
2014-09-09 22:21 ` Ard Biesheuvel
2014-09-10 15:42 ` Greg Bellows
2014-09-10 16:13 ` Ard Biesheuvel
2014-09-10 16:17 ` Peter Maydell
2014-09-10 16:29 ` Greg Bellows
2014-09-05 12:24 ` [Qemu-devel] [PATCH v3 4/6] target-arm: add missing PSCI constants needed for PSCI emulation Ard Biesheuvel
2014-09-09 15:28 ` Peter Maydell
2014-09-09 15:34 ` Ard Biesheuvel
2014-09-09 15:43 ` Peter Maydell
2014-09-05 12:24 ` [Qemu-devel] [PATCH v3 5/6] target-arm: add emulation of PSCI calls for system emulation Ard Biesheuvel
2014-09-09 17:17 ` Peter Maydell
2014-09-09 17:33 ` Ard Biesheuvel
2014-09-05 12:24 ` [Qemu-devel] [PATCH v3 6/6] arm/virt: enable PSCI emulation support " Ard Biesheuvel
2014-09-09 16:10 ` Peter Maydell
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