From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:54218) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1XRKZQ-0002WA-Ip for qemu-devel@nongnu.org; Tue, 09 Sep 2014 08:30:58 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1XRKZK-0003An-4N for qemu-devel@nongnu.org; Tue, 09 Sep 2014 08:30:52 -0400 Received: from mail-qg0-x22a.google.com ([2607:f8b0:400d:c04::22a]:56678) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1XRKZJ-0003AZ-UF for qemu-devel@nongnu.org; Tue, 09 Sep 2014 08:30:46 -0400 Received: by mail-qg0-f42.google.com with SMTP id q107so7286041qgd.1 for ; Tue, 09 Sep 2014 05:30:45 -0700 (PDT) Sender: Paolo Bonzini From: Paolo Bonzini Date: Tue, 9 Sep 2014 14:30:08 +0200 Message-Id: <1410265809-27247-10-git-send-email-pbonzini@redhat.com> In-Reply-To: <1410265809-27247-1-git-send-email-pbonzini@redhat.com> References: <1410265809-27247-1-git-send-email-pbonzini@redhat.com> Subject: [Qemu-devel] [PATCH 09/10] piix: do not raise irq while loading vmstate List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org Cc: amit.shah@redhat.com, dgilbert@redhat.com, Pavel.Dovgaluk@ispras.ru, quintela@redhat.com From: Pavel Dovgalyuk This patch disables raising an irq while loading the state of PCI bridge. The aim of this patch is preserving the same behavior while saving and restoring the VM state. IRQ is not raised while saving the state of the bridge. That's why the behavior of the restored system will differ from the original one. This patch eliminates raising an irq and just restores the calculated state fields in post_load function. Signed-off-by: Pavel Dovgalyuk Signed-off-by: Paolo Bonzini --- hw/pci-host/piix.c | 26 ++++++++++++++++++++++++-- 1 file changed, 24 insertions(+), 2 deletions(-) diff --git a/hw/pci-host/piix.c b/hw/pci-host/piix.c index e0e0946..cd50435 100644 --- a/hw/pci-host/piix.c +++ b/hw/pci-host/piix.c @@ -409,7 +409,7 @@ static void piix3_set_irq_pic(PIIX3State *piix3, int pic_irq) (pic_irq * PIIX_NUM_PIRQS)))); } -static void piix3_set_irq_level(PIIX3State *piix3, int pirq, int level) +static void piix3_set_irq_level_internal(PIIX3State *piix3, int pirq, int level) { int pic_irq; uint64_t mask; @@ -422,6 +422,18 @@ static void piix3_set_irq_level(PIIX3State *piix3, int pirq, int level) mask = 1ULL << ((pic_irq * PIIX_NUM_PIRQS) + pirq); piix3->pic_levels &= ~mask; piix3->pic_levels |= mask * !!level; +} + +static void piix3_set_irq_level(PIIX3State *piix3, int pirq, int level) +{ + int pic_irq; + + pic_irq = piix3->dev.config[PIIX_PIRQC + pirq]; + if (pic_irq >= PIIX_NUM_PIC_IRQS) { + return; + } + + piix3_set_irq_level_internal(piix3, pirq, level); piix3_set_irq_pic(piix3, pic_irq); } @@ -527,7 +539,18 @@ static void piix3_reset(void *opaque) static int piix3_post_load(void *opaque, int version_id) { PIIX3State *piix3 = opaque; - piix3_update_irq_levels(piix3); + int pirq; + + /* Update irq levels without raising an interrupt which could + * happen in piix3_update_irq_levels. Raising an IRQ will + * bring the system to a different state than the saved one. + * Interrupt state is serialized separately through the i8259. + */ + piix3->pic_levels = 0; + for (pirq = 0; pirq < PIIX_NUM_PIRQS; pirq++) { + piix3_set_irq_level_internal(piix3, pirq, + pci_bus_get_irq_level(piix3->dev.bus, pirq)); + } return 0; } -- 2.1.0