[Qemu-devel] [PATCH 0/2] target-arm: Implement TLB invalidate inner shareable ops properly

[Peter Maydell <peter.maydell@linaro.org>]

The ARM architecture defines that the "IS" variants of TLB
maintenance operations must affect all TLBs in the Inner Shareable
domain, which for us means all CPUs. We were incorrectly implementing
these to only affect the current CPU, which meant that SMP TCG
operation was unstable (especially noticeable on v8).

These patches shove the legacy loosely-decoded wildcard TLB
op definitions back from "not-v8" to "not-v7" so we can
use the correct strict decode for v7 and v7MP (which is
where the IS ops were introduced); this then gives us a
place we can insert the correct behaviour.

Without these patches, using Ard's PSCI emulation patches
with lots of SMP CPUs tends to result in Oopses, processes
crashing with illegal instruction exceptions, etc.

Although we don't support SMP TCG in QEMU 2.1, I've
cc'd these to stable because they also affect v7.

Peter Maydell (2):
  target-arm: Push legacy wildcard TLB ops back into v6
  target-arm: Make *IS TLB maintenance ops affect all CPUs

 target-arm/helper.c | 195 +++++++++++++++++++++++++++++++++++++---------------
 1 file changed, 140 insertions(+), 55 deletions(-)

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1.9.1