From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:44918) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1XS9y8-00060A-1J for qemu-devel@nongnu.org; Thu, 11 Sep 2014 15:23:58 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1XS9xy-0005j2-Pq for qemu-devel@nongnu.org; Thu, 11 Sep 2014 15:23:47 -0400 From: Pierre Mallard Date: Thu, 11 Sep 2014 21:17:43 +0200 Message-Id: <1410463065-4400-1-git-send-email-mallard.pierre@gmail.com> In-Reply-To: <1410325413> References: <1410325413> Subject: [Qemu-devel] [PATCH 0/2] Enabling floating point instruction to 440x5 CPUs List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org, qemu-ppc@nongnu.org Cc: tommusta@gmail.com, agraf@suse.de, Pierre Mallard This patch series enable floating point instruction in 440x5 CPUs which have the capabilities to have optional APU FPU in double precision mode. 1) Allow fc[tf]id[*] mnemonics for non TARGET_PPC64 with a new insn2 flag 2) Create a new 440x5 implementing floating point instructions Pierre Mallard (2): target-ppc : Allow fc[tf]id[*] mnemonics for non TARGET_PPC64 target-ppc : Add new processor type 440x5wDFPU target-ppc/cpu-models.c | 3 +++ target-ppc/cpu.h | 5 ++++- target-ppc/fpu_helper.c | 6 ------ target-ppc/helper.h | 4 +--- target-ppc/translate.c | 18 +++++++---------- target-ppc/translate_init.c | 47 ++++++++++++++++++++++++++++++++++++++++--- 6 files changed, 59 insertions(+), 24 deletions(-) -- 1.7.10.4