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From: Peter Maydell <peter.maydell@linaro.org>
To: qemu-devel@nongnu.org
Subject: [Qemu-devel] [PULL 12/23] target-arm: Move extended_addresses_enabled() to internals.h
Date: Fri, 12 Sep 2014 14:23:43 +0100	[thread overview]
Message-ID: <1410528234-13545-13-git-send-email-peter.maydell@linaro.org> (raw)
In-Reply-To: <1410528234-13545-1-git-send-email-peter.maydell@linaro.org>

Move the utility function extended_addresses_enabled() into
internals.h; we're going to need to call it from op_helper.c.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 target-arm/helper.c    | 11 -----------
 target-arm/internals.h | 11 +++++++++++
 2 files changed, 11 insertions(+), 11 deletions(-)

diff --git a/target-arm/helper.c b/target-arm/helper.c
index 103dfb8..5fd5497 100644
--- a/target-arm/helper.c
+++ b/target-arm/helper.c
@@ -304,17 +304,6 @@ void init_cpreg_list(ARMCPU *cpu)
     g_list_free(keys);
 }
 
-/* Return true if extended addresses are enabled.
- * This is always the case if our translation regime is 64 bit,
- * but depends on TTBCR.EAE for 32 bit.
- */
-static inline bool extended_addresses_enabled(CPUARMState *env)
-{
-    return arm_el_is_aa64(env, 1)
-        || ((arm_feature(env, ARM_FEATURE_LPAE)
-             && (env->cp15.c2_control & TTBCR_EAE)));
-}
-
 static void dacr_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value)
 {
     ARMCPU *cpu = arm_env_get_cpu(env);
diff --git a/target-arm/internals.h b/target-arm/internals.h
index 22f382c..1d788b0 100644
--- a/target-arm/internals.h
+++ b/target-arm/internals.h
@@ -142,6 +142,17 @@ static inline void update_spsel(CPUARMState *env, uint32_t imm)
     aarch64_restore_sp(env, cur_el);
 }
 
+/* Return true if extended addresses are enabled.
+ * This is always the case if our translation regime is 64 bit,
+ * but depends on TTBCR.EAE for 32 bit.
+ */
+static inline bool extended_addresses_enabled(CPUARMState *env)
+{
+    return arm_el_is_aa64(env, 1)
+        || ((arm_feature(env, ARM_FEATURE_LPAE)
+             && (env->cp15.c2_control & TTBCR_EAE)));
+}
+
 /* Valid Syndrome Register EC field values */
 enum arm_exception_class {
     EC_UNCATEGORIZED          = 0x00,
-- 
1.9.1

  parent reply	other threads:[~2014-09-12 13:24 UTC|newest]

Thread overview: 27+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2014-09-12 13:23 [Qemu-devel] [PULL 00/23] target-arm queue Peter Maydell
2014-09-12 13:23 ` [Qemu-devel] [PULL 01/23] hw/arm/virt: add linux, stdout-path to /chosen DT node Peter Maydell
2014-09-12 13:23 ` [Qemu-devel] [PULL 02/23] cpu-exec.c: Allow disabling of IRQs on ARM Cortex-M CPUs Peter Maydell
2014-09-12 13:23 ` [Qemu-devel] [PULL 03/23] pl061: implement input interrupt logic Peter Maydell
2014-09-12 13:23 ` [Qemu-devel] [PULL 04/23] target-arm: Fix resetting issues on ARMv7-M CPUs Peter Maydell
2014-09-12 13:23 ` [Qemu-devel] [PULL 05/23] target-arm: Fix broken indentation in arm_cpu_reest() Peter Maydell
2014-09-12 13:23 ` [Qemu-devel] [PULL 06/23] hw/arm/virt: Provide flash devices for boot ROMs Peter Maydell
2014-09-12 13:23 ` [Qemu-devel] [PULL 07/23] exec.c: Relax restrictions on watchpoint length and alignment Peter Maydell
2014-09-18  4:48   ` Max Filippov
2014-09-18  4:58     ` Peter Maydell
2014-09-12 13:23 ` [Qemu-devel] [PULL 08/23] exec.c: Provide full set of dummy wp remove functions in user-mode Peter Maydell
2014-09-12 13:23 ` [Qemu-devel] [PULL 09/23] exec.c: Record watchpoint fault address and direction Peter Maydell
2014-09-12 13:23 ` [Qemu-devel] [PULL 10/23] cpu-exec: Make debug_excp_handler a QOM CPU method Peter Maydell
2014-09-12 13:23 ` [Qemu-devel] [PULL 11/23] target-arm: Implement setting of watchpoints Peter Maydell
2014-09-12 13:23 ` Peter Maydell [this message]
2014-09-12 13:23 ` [Qemu-devel] [PULL 13/23] target-arm: Implement handling of fired watchpoints Peter Maydell
2014-09-12 13:23 ` [Qemu-devel] [PULL 14/23] target-arm: Set DBGDSCR.MOE for debug exceptions taken to AArch32 Peter Maydell
2014-09-12 13:23 ` [Qemu-devel] [PULL 15/23] target-arm: Remove comment about MDSCR_EL1 being dummy implementation Peter Maydell
2014-09-12 13:23 ` [Qemu-devel] [PULL 16/23] target-arm: Implement minimal DBGVCR, OSDLR_EL1, MDCCSR_EL0 Peter Maydell
2014-09-12 13:23 ` [Qemu-devel] [PULL 17/23] target-arm: Push legacy wildcard TLB ops back into v6 Peter Maydell
2014-09-12 13:23 ` [Qemu-devel] [PULL 18/23] target-arm: Make *IS TLB maintenance ops affect all CPUs Peter Maydell
2014-09-12 13:23 ` [Qemu-devel] [PULL 19/23] hw/arm/virt: fix pl011 and pl031 irq flags Peter Maydell
2014-09-12 13:23 ` [Qemu-devel] [PULL 20/23] hw/arm/boot: load DTB as a ROM image Peter Maydell
2014-09-12 13:23 ` [Qemu-devel] [PULL 21/23] hw/arm/boot: pass an address limit to and return size from load_dtb() Peter Maydell
2014-09-12 13:23 ` [Qemu-devel] [PULL 22/23] hw/arm/boot: load device tree to base of DRAM if no -kernel option was passed Peter Maydell
2014-09-12 13:23 ` [Qemu-devel] [PULL 23/23] hw/arm/boot: enable DTB support when booting ELF images Peter Maydell
2014-09-12 15:55 ` [Qemu-devel] [PULL 00/23] target-arm queue Peter Maydell

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