From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:57018) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1XSQpb-0006q9-NQ for qemu-devel@nongnu.org; Fri, 12 Sep 2014 09:24:15 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1XSQpT-00040O-7w for qemu-devel@nongnu.org; Fri, 12 Sep 2014 09:24:07 -0400 Received: from mnementh.archaic.org.uk ([81.2.115.146]:46960) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1XSQpT-0003xI-0w for qemu-devel@nongnu.org; Fri, 12 Sep 2014 09:23:59 -0400 Received: from pm215 by mnementh.archaic.org.uk with local (Exim 4.80) (envelope-from ) id 1XSQpO-0003X4-Fv for qemu-devel@nongnu.org; Fri, 12 Sep 2014 14:23:54 +0100 From: Peter Maydell Date: Fri, 12 Sep 2014 14:23:33 +0100 Message-Id: <1410528234-13545-3-git-send-email-peter.maydell@linaro.org> In-Reply-To: <1410528234-13545-1-git-send-email-peter.maydell@linaro.org> References: <1410528234-13545-1-git-send-email-peter.maydell@linaro.org> Subject: [Qemu-devel] [PULL 02/23] cpu-exec.c: Allow disabling of IRQs on ARM Cortex-M CPUs List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org From: David Hoover Correct an error in the logic for deciding whether we can take an IRQ interrupt which meant that on M profile cores it was never possible to disable them. The design here is still bogus in that M profile doesn't have separate "IRQ" and "FIQ", which are an A/R profile concept; we should ideally implement the proper priority based scheme. Signed-off-by: David Hoover [PMM: Wrote a proper commit message] Signed-off-by: Peter Maydell --- cpu-exec.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/cpu-exec.c b/cpu-exec.c index 7b5d2e2..e9adf56 100644 --- a/cpu-exec.c +++ b/cpu-exec.c @@ -618,8 +618,8 @@ int cpu_exec(CPUArchState *env) We avoid this by disabling interrupts when pc contains a magic address. */ if (interrupt_request & CPU_INTERRUPT_HARD - && ((IS_M(env) && env->regs[15] < 0xfffffff0) - || !(env->daif & PSTATE_I))) { + && !(env->daif & PSTATE_I) + && (!IS_M(env) || env->regs[15] < 0xfffffff0)) { cpu->exception_index = EXCP_IRQ; cc->do_interrupt(cpu); next_tb = 0; -- 1.9.1