From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:37277) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1XSROC-0006X7-OC for qemu-devel@nongnu.org; Fri, 12 Sep 2014 09:59:58 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1XSRO4-00010L-3D for qemu-devel@nongnu.org; Fri, 12 Sep 2014 09:59:52 -0400 Received: from mail-qg0-x236.google.com ([2607:f8b0:400d:c04::236]:40776) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1XSRO3-000104-Uw for qemu-devel@nongnu.org; Fri, 12 Sep 2014 09:59:44 -0400 Received: by mail-qg0-f54.google.com with SMTP id z60so761120qgd.27 for ; Fri, 12 Sep 2014 06:59:43 -0700 (PDT) Sender: Paolo Bonzini From: Paolo Bonzini Date: Fri, 12 Sep 2014 15:58:55 +0200 Message-Id: <1410530338-17615-19-git-send-email-pbonzini@redhat.com> In-Reply-To: <1410530338-17615-1-git-send-email-pbonzini@redhat.com> References: <1410530338-17615-1-git-send-email-pbonzini@redhat.com> Subject: [Qemu-devel] [PULL 18/21] piix: do not set irq while loading vmstate List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org Cc: Pavel Dovgalyuk From: Pavel Dovgalyuk This patch avoids setting an irq while loading the state of the ISA bridge. Because the i8259 has not been deserialized yet, raising an interrupt could bring the system out-of-sync with the migration source. For example, the migration source could have masked the interrupt in the i8259. On the destination, the i8259 device model would not know that yet and would trigger an interrupt in the CPU. This patch eliminates setting the irq and just restores the calculated state fields in post_load function. Interrupt state will be deserialized separately through the IRR field of the i8259. Signed-off-by: Pavel Dovgalyuk Reviewed-by: Michael S. Tsirkin Signed-off-by: Paolo Bonzini --- hw/pci-host/piix.c | 30 ++++++++++++++++++++++++++++-- 1 file changed, 28 insertions(+), 2 deletions(-) diff --git a/hw/pci-host/piix.c b/hw/pci-host/piix.c index e0e0946..1530038 100644 --- a/hw/pci-host/piix.c +++ b/hw/pci-host/piix.c @@ -409,7 +409,7 @@ static void piix3_set_irq_pic(PIIX3State *piix3, int pic_irq) (pic_irq * PIIX_NUM_PIRQS)))); } -static void piix3_set_irq_level(PIIX3State *piix3, int pirq, int level) +static void piix3_set_irq_level_internal(PIIX3State *piix3, int pirq, int level) { int pic_irq; uint64_t mask; @@ -422,6 +422,18 @@ static void piix3_set_irq_level(PIIX3State *piix3, int pirq, int level) mask = 1ULL << ((pic_irq * PIIX_NUM_PIRQS) + pirq); piix3->pic_levels &= ~mask; piix3->pic_levels |= mask * !!level; +} + +static void piix3_set_irq_level(PIIX3State *piix3, int pirq, int level) +{ + int pic_irq; + + pic_irq = piix3->dev.config[PIIX_PIRQC + pirq]; + if (pic_irq >= PIIX_NUM_PIC_IRQS) { + return; + } + + piix3_set_irq_level_internal(piix3, pirq, level); piix3_set_irq_pic(piix3, pic_irq); } @@ -527,7 +539,21 @@ static void piix3_reset(void *opaque) static int piix3_post_load(void *opaque, int version_id) { PIIX3State *piix3 = opaque; - piix3_update_irq_levels(piix3); + int pirq; + + /* Because the i8259 has not been deserialized yet, qemu_irq_raise + * might bring the system to a different state than the saved one; + * for example, the interrupt could be masked but the i8259 would + * not know that yet and would trigger an interrupt in the CPU. + * + * Here, we update irq levels without raising the interrupt. + * Interrupt state will be deserialized separately through the i8259. + */ + piix3->pic_levels = 0; + for (pirq = 0; pirq < PIIX_NUM_PIRQS; pirq++) { + piix3_set_irq_level_internal(piix3, pirq, + pci_bus_get_irq_level(piix3->dev.bus, pirq)); + } return 0; } -- 2.1.0