From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:54568) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1XSWaR-0006zm-2G for qemu-devel@nongnu.org; Fri, 12 Sep 2014 15:33:00 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1XSWaF-0005TV-1Q for qemu-devel@nongnu.org; Fri, 12 Sep 2014 15:32:51 -0400 From: Pierre Mallard Date: Fri, 12 Sep 2014 21:31:33 +0200 Message-Id: <1410550293-3814-3-git-send-email-mallard.pierre@gmail.com> In-Reply-To: <1410550293-3814-1-git-send-email-mallard.pierre@gmail.com> References: <1410325413> <1410550293-3814-1-git-send-email-mallard.pierre@gmail.com> Subject: [Qemu-devel] [PATCH v2 2/2] target-ppc : Add new processor type 440x5wDFPU List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org, qemu-ppc@nongnu.org Cc: agraf@suze.de, tommusta@gmail.com, Pierre Mallard This patch add a new processor type 440x5wDFPU for Virtex 5 PPC440 with an external APU FPU in double precision mode Signed-off-by: Pierre Mallard --- target-ppc/cpu-models.c | 3 +++ target-ppc/translate_init.c | 38 ++++++++++++++++++++++++++++++++++++++ 2 files changed, 41 insertions(+) diff --git a/target-ppc/cpu-models.c b/target-ppc/cpu-models.c index 52ac6ec..3f18996 100644 --- a/target-ppc/cpu-models.c +++ b/target-ppc/cpu-models.c @@ -309,6 +309,9 @@ #endif POWERPC_DEF("440-Xilinx", CPU_POWERPC_440_XILINX, 440x5, "PowerPC 440 Xilinx 5") + + POWERPC_DEF("440-Xilinx-w-dfpu", CPU_POWERPC_440_XILINX, 440x5wDFPU, + "PowerPC 440 Xilinx 5 With a Double Prec. FPU") #if defined(TODO) POWERPC_DEF("440A5", CPU_POWERPC_440A5, 440x5, "PowerPC 440 A5") diff --git a/target-ppc/translate_init.c b/target-ppc/translate_init.c index ac4d12a..4baf1f3 100644 --- a/target-ppc/translate_init.c +++ b/target-ppc/translate_init.c @@ -3923,6 +3923,44 @@ POWERPC_FAMILY(440x5)(ObjectClass *oc, void *data) POWERPC_FLAG_DE | POWERPC_FLAG_BUS_CLK; } +POWERPC_FAMILY(440x5wDFPU)(ObjectClass *oc, void *data) +{ + DeviceClass *dc = DEVICE_CLASS(oc); + PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); + + dc->desc = "PowerPC 440x5 with double precision FPU"; + pcc->init_proc = init_proc_440x5; + pcc->check_pow = check_pow_nocheck; + pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | + PPC_FLOAT | PPC_FLOAT_FSQRT | + PPC_FLOAT_STFIWX | + PPC_DCR | PPC_WRTEE | PPC_RFMCI | + PPC_CACHE | PPC_CACHE_ICBI | + PPC_CACHE_DCBZ | PPC_CACHE_DCBA | + PPC_MEM_TLBSYNC | PPC_MFTB | + PPC_BOOKE | PPC_4xx_COMMON | PPC_405_MAC | + PPC_440_SPEC; + pcc->insns_flags2 = PPC2_FP_CVT_S64; + pcc->msr_mask = (1ull << MSR_POW) | + (1ull << MSR_CE) | + (1ull << MSR_EE) | + (1ull << MSR_PR) | + (1ull << MSR_FP) | + (1ull << MSR_ME) | + (1ull << MSR_FE0) | + (1ull << MSR_DWE) | + (1ull << MSR_DE) | + (1ull << MSR_FE1) | + (1ull << MSR_IR) | + (1ull << MSR_DR); + pcc->mmu_model = POWERPC_MMU_BOOKE; + pcc->excp_model = POWERPC_EXCP_BOOKE; + pcc->bus_model = PPC_FLAGS_INPUT_BookE; + pcc->bfd_mach = bfd_mach_ppc_403; + pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_DWE | + POWERPC_FLAG_DE | POWERPC_FLAG_BUS_CLK; +} + static void init_proc_460 (CPUPPCState *env) { /* Time base */ -- 1.7.10.4