From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:38745) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1XSf45-0007YF-BR for qemu-devel@nongnu.org; Sat, 13 Sep 2014 00:36:06 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1XSf3w-0006ML-Id for qemu-devel@nongnu.org; Sat, 13 Sep 2014 00:36:01 -0400 Received: from mail-qc0-x230.google.com ([2607:f8b0:400d:c01::230]:59032) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1XSf3w-0006MH-F7 for qemu-devel@nongnu.org; Sat, 13 Sep 2014 00:35:52 -0400 Received: by mail-qc0-f176.google.com with SMTP id x3so1948445qcv.7 for ; Fri, 12 Sep 2014 21:35:52 -0700 (PDT) From: "Edgar E. Iglesias" Date: Sat, 13 Sep 2014 14:29:18 +1000 Message-Id: <1410582564-27687-5-git-send-email-edgar.iglesias@gmail.com> In-Reply-To: <1410582564-27687-1-git-send-email-edgar.iglesias@gmail.com> References: <1410582564-27687-1-git-send-email-edgar.iglesias@gmail.com> Subject: [Qemu-devel] [PATCH v6 04/10] target-arm: Break out exception masking to a separate func List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org, peter.maydell@linaro.org Cc: rob.herring@linaro.org, peter.crosthwaite@xilinx.com, aggelerf@ethz.ch, agraf@suse.de, greg.bellows@linaro.org, pbonzini@redhat.com, alex.bennee@linaro.org, christoffer.dall@linaro.org, rth@twiddle.net From: "Edgar E. Iglesias" Reviewed-by: Greg Bellows Signed-off-by: Edgar E. Iglesias --- cpu-exec.c | 5 ++--- target-arm/cpu.h | 15 +++++++++++++++ 2 files changed, 17 insertions(+), 3 deletions(-) diff --git a/cpu-exec.c b/cpu-exec.c index bd93165..d017588 100644 --- a/cpu-exec.c +++ b/cpu-exec.c @@ -596,7 +596,7 @@ int cpu_exec(CPUArchState *env) } #elif defined(TARGET_ARM) if (interrupt_request & CPU_INTERRUPT_FIQ - && !(env->daif & PSTATE_F)) { + && arm_excp_unmasked(cpu, EXCP_FIQ)) { cpu->exception_index = EXCP_FIQ; cc->do_interrupt(cpu); next_tb = 0; @@ -611,8 +611,7 @@ int cpu_exec(CPUArchState *env) We avoid this by disabling interrupts when pc contains a magic address. */ if (interrupt_request & CPU_INTERRUPT_HARD - && !(env->daif & PSTATE_I) - && (!IS_M(env) || env->regs[15] < 0xfffffff0)) { + && arm_excp_unmasked(cpu, EXCP_IRQ)) { cpu->exception_index = EXCP_IRQ; cc->do_interrupt(cpu); next_tb = 0; diff --git a/target-arm/cpu.h b/target-arm/cpu.h index e2474d0..a5e8e0d 100644 --- a/target-arm/cpu.h +++ b/target-arm/cpu.h @@ -1171,6 +1171,21 @@ bool write_cpustate_to_list(ARMCPU *cpu); # define TARGET_VIRT_ADDR_SPACE_BITS 32 #endif +static inline bool arm_excp_unmasked(CPUState *cs, unsigned int excp_idx) +{ + CPUARMState *env = cs->env_ptr; + + switch (excp_idx) { + case EXCP_FIQ: + return !(env->daif & PSTATE_F); + case EXCP_IRQ: + return !(env->daif & PSTATE_I) + && (!IS_M(env) || env->regs[15] < 0xfffffff0); + default: + g_assert_not_reached(); + } +} + static inline CPUARMState *cpu_init(const char *cpu_model) { ARMCPU *cpu = cpu_arm_init(cpu_model); -- 1.9.1