From: "Edgar E. Iglesias" <edgar.iglesias@gmail.com>
To: qemu-devel@nongnu.org, peter.maydell@linaro.org
Cc: rob.herring@linaro.org, peter.crosthwaite@xilinx.com,
aggelerf@ethz.ch, agraf@suse.de, greg.bellows@linaro.org,
pbonzini@redhat.com, alex.bennee@linaro.org,
christoffer.dall@linaro.org, rth@twiddle.net
Subject: [Qemu-devel] [PATCH v6 05/10] target-arm: Don't take interrupts targeting lower ELs
Date: Sat, 13 Sep 2014 14:29:19 +1000 [thread overview]
Message-ID: <1410582564-27687-6-git-send-email-edgar.iglesias@gmail.com> (raw)
In-Reply-To: <1410582564-27687-1-git-send-email-edgar.iglesias@gmail.com>
From: "Edgar E. Iglesias" <edgar.iglesias@xilinx.com>
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Reviewed-by: Greg Bellows <greg.bellows@linaro.org>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
---
target-arm/cpu.h | 7 +++++++
1 file changed, 7 insertions(+)
diff --git a/target-arm/cpu.h b/target-arm/cpu.h
index a5e8e0d..7f8a410 100644
--- a/target-arm/cpu.h
+++ b/target-arm/cpu.h
@@ -1174,6 +1174,13 @@ bool write_cpustate_to_list(ARMCPU *cpu);
static inline bool arm_excp_unmasked(CPUState *cs, unsigned int excp_idx)
{
CPUARMState *env = cs->env_ptr;
+ unsigned int cur_el = arm_current_pl(env);
+ unsigned int target_el = arm_excp_target_el(cs, excp_idx);
+
+ /* Don't take exceptions if they target a lower EL. */
+ if (cur_el > target_el) {
+ return false;
+ }
switch (excp_idx) {
case EXCP_FIQ:
--
1.9.1
next prev parent reply other threads:[~2014-09-13 4:36 UTC|newest]
Thread overview: 34+ messages / expand[flat|nested] mbox.gz Atom feed top
2014-09-13 4:29 [Qemu-devel] [PATCH v6 00/10] target-arm: Parts of the AArch64 EL2/3 exception model Edgar E. Iglesias
2014-09-13 4:29 ` [Qemu-devel] [PATCH v6 01/10] target-arm: Add HCR_EL2 Edgar E. Iglesias
2014-09-13 4:29 ` [Qemu-devel] [PATCH v6 02/10] target-arm: Add SCR_EL3 Edgar E. Iglesias
2014-09-17 15:49 ` Greg Bellows
2014-09-25 18:15 ` Peter Maydell
2014-09-25 19:49 ` Greg Bellows
2014-09-25 19:53 ` Peter Maydell
2014-09-25 20:00 ` Greg Bellows
2014-09-25 22:12 ` Edgar E. Iglesias
2014-09-13 4:29 ` [Qemu-devel] [PATCH v6 03/10] target-arm: A64: Refactor aarch64_cpu_do_interrupt Edgar E. Iglesias
2014-09-13 4:29 ` [Qemu-devel] [PATCH v6 04/10] target-arm: Break out exception masking to a separate func Edgar E. Iglesias
2014-09-13 4:29 ` Edgar E. Iglesias [this message]
2014-09-13 4:29 ` [Qemu-devel] [PATCH v6 06/10] target-arm: A64: Correct updates to FAR and ESR on exceptions Edgar E. Iglesias
2014-09-13 4:29 ` [Qemu-devel] [PATCH v6 07/10] target-arm: A64: Emulate the HVC insn Edgar E. Iglesias
2014-09-17 21:47 ` Greg Bellows
2014-09-25 18:39 ` Peter Maydell
2014-09-25 22:20 ` Edgar E. Iglesias
2014-09-25 23:01 ` Peter Maydell
2014-09-25 23:06 ` Edgar E. Iglesias
2014-09-25 23:19 ` Peter Maydell
2014-09-13 4:29 ` [Qemu-devel] [PATCH v6 08/10] target-arm: A64: Emulate the SMC insn Edgar E. Iglesias
2014-09-17 22:43 ` Greg Bellows
2014-09-25 18:47 ` Peter Maydell
2014-09-25 22:55 ` Edgar E. Iglesias
2014-09-25 23:17 ` Peter Maydell
2014-09-25 23:31 ` Edgar E. Iglesias
2014-09-25 23:43 ` Peter Maydell
2014-09-25 23:45 ` Edgar E. Iglesias
2014-09-26 8:20 ` Edgar E. Iglesias
2014-09-13 4:29 ` [Qemu-devel] [PATCH v6 09/10] target-arm: Add IRQ and FIQ routing to EL2 and 3 Edgar E. Iglesias
2014-09-25 19:14 ` Peter Maydell
2014-09-13 4:29 ` [Qemu-devel] [PATCH v6 10/10] target-arm: Add support for VIRQ and VFIQ Edgar E. Iglesias
2014-09-25 19:36 ` Peter Maydell
2014-09-25 23:03 ` Edgar E. Iglesias
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