From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:47287) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1XSqSR-0001Wj-G0 for qemu-devel@nongnu.org; Sat, 13 Sep 2014 12:46:00 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1XSqSM-0000l7-Kw for qemu-devel@nongnu.org; Sat, 13 Sep 2014 12:45:55 -0400 Received: from mail-pa0-x22e.google.com ([2607:f8b0:400e:c03::22e]:58150) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1XSqSM-0000kz-Bd for qemu-devel@nongnu.org; Sat, 13 Sep 2014 12:45:50 -0400 Received: by mail-pa0-f46.google.com with SMTP id kq14so3507667pab.5 for ; Sat, 13 Sep 2014 09:45:49 -0700 (PDT) Sender: Richard Henderson From: Richard Henderson Date: Sat, 13 Sep 2014 09:45:17 -0700 Message-Id: <1410626734-3804-7-git-send-email-rth@twiddle.net> In-Reply-To: <1410626734-3804-1-git-send-email-rth@twiddle.net> References: <1410626734-3804-1-git-send-email-rth@twiddle.net> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Subject: [Qemu-devel] [PATCH 06/23] qom: Add cpu_exec_interrupt hook List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org Cc: peter.maydell@linaro.org, afaerber@suse.de, aliguori@amazon.com Continuing the removal of ifdefs from cpu_exec. Cc: Andreas Färber Signed-off-by: Richard Henderson --- cpu-exec.c | 14 +++++++++----- include/qom/cpu.h | 2 ++ qom/cpu.c | 6 ++++++ 3 files changed, 17 insertions(+), 5 deletions(-) diff --git a/cpu-exec.c b/cpu-exec.c index d930e7a..fe313b4 100644 --- a/cpu-exec.c +++ b/cpu-exec.c @@ -676,8 +676,15 @@ int cpu_exec(CPUArchState *env) next_tb = 0; } #endif - /* Don't use the cached interrupt_request value, - do_interrupt may have updated the EXITTB flag. */ + /* The target hook has 3 exit conditions: + False when the interrupt isn't processed, + True when it is, and we should restart on a new TB, + and via longjmp via cpu_loop_exit. */ + if (cc->cpu_exec_interrupt(cpu, interrupt_request)) { + next_tb = 0; + } + /* Don't use the cached interrupt_request value, + do_interrupt may have updated the EXITTB flag. */ if (cpu->interrupt_request & CPU_INTERRUPT_EXITTB) { cpu->interrupt_request &= ~CPU_INTERRUPT_EXITTB; /* ensure that no TB jump will be modified as @@ -783,10 +790,7 @@ int cpu_exec(CPUArchState *env) * local variables as longjmp is marked 'noreturn'. */ cpu = current_cpu; env = cpu->env_ptr; -#if !(defined(CONFIG_USER_ONLY) && \ - (defined(TARGET_M68K) || defined(TARGET_PPC) || defined(TARGET_S390X))) cc = CPU_GET_CLASS(cpu); -#endif #ifdef TARGET_I386 x86_cpu = X86_CPU(cpu); #endif diff --git a/include/qom/cpu.h b/include/qom/cpu.h index 0340cf4..f576b47 100644 --- a/include/qom/cpu.h +++ b/include/qom/cpu.h @@ -101,6 +101,7 @@ struct TranslationBlock; * @gdb_core_xml_file: File name for core registers GDB XML description. * @cpu_exec_enter: Callback for cpu_exec preparation. * @cpu_exec_exit: Callback for cpu_exec cleanup. + * @cpu_exec_interrupt: Callback for processing interrupts in cpu_exec. * * Represents a CPU family or model. */ @@ -154,6 +155,7 @@ typedef struct CPUClass { void (*cpu_exec_enter)(CPUState *cpu); void (*cpu_exec_exit)(CPUState *cpu); + bool (*cpu_exec_interrupt)(CPUState *cpu, int interrupt_request); } CPUClass; #ifdef HOST_WORDS_BIGENDIAN diff --git a/qom/cpu.c b/qom/cpu.c index 6a9d02e..0ec3337 100644 --- a/qom/cpu.c +++ b/qom/cpu.c @@ -206,6 +206,11 @@ static void cpu_common_noop(CPUState *cpu) { } +static bool cpu_common_exec_interrupt(CPUState *cpu, int int_req) +{ + return false; +} + void cpu_dump_state(CPUState *cpu, FILE *f, fprintf_function cpu_fprintf, int flags) { @@ -347,6 +352,7 @@ static void cpu_class_init(ObjectClass *klass, void *data) k->debug_excp_handler = cpu_common_noop; k->cpu_exec_enter = cpu_common_noop; k->cpu_exec_exit = cpu_common_noop; + k->cpu_exec_interrupt = cpu_common_exec_interrupt; dc->realize = cpu_common_realizefn; /* * Reason: CPUs still need special care by board code: wiring up -- 1.9.3