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From: Paolo Bonzini <pbonzini@redhat.com>
To: qemu-devel@nongnu.org
Cc: tommusta@gmail.com, agraf@suse.de
Subject: [Qemu-devel] [PATCH 04/14] ppc: introduce ppc_get_cr and ppc_set_cr
Date: Mon, 15 Sep 2014 17:03:31 +0200	[thread overview]
Message-ID: <1410793421-6453-5-git-send-email-pbonzini@redhat.com> (raw)
In-Reply-To: <1410793421-6453-1-git-send-email-pbonzini@redhat.com>

New functions to put together all 32 CR bits.  Avoids easy
off-by-one mistakes such as the one fixed by commit f13f529
(ppc: fix monitor access to CR, 2014-08-28).

Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
---
	v1->v2: replaces "ppc: use ARRAY_SIZE in gdbstub.c"

 linux-user/elfload.c |  4 +---
 linux-user/signal.c  |  8 ++------
 monitor.c            |  9 +--------
 target-ppc/cpu.h     | 20 ++++++++++++++++++++
 target-ppc/gdbstub.c | 42 ++++++++----------------------------------
 target-ppc/kvm.c     | 11 ++---------
 6 files changed, 34 insertions(+), 60 deletions(-)

diff --git a/linux-user/elfload.c b/linux-user/elfload.c
index bea803b..a7d1714 100644
--- a/linux-user/elfload.c
+++ b/linux-user/elfload.c
@@ -857,9 +857,7 @@ static void elf_core_copy_regs(target_elf_gregset_t *regs, const CPUPPCState *en
     (*regs)[36] = tswapreg(env->lr);
     (*regs)[37] = tswapreg(env->xer);
 
-    for (i = 0; i < ARRAY_SIZE(env->crf); i++) {
-        ccr |= env->crf[i] << (32 - ((i + 1) * 4));
-    }
+    ccr = ppc_get_cr(env);
     (*regs)[38] = tswapreg(ccr);
 }
 
diff --git a/linux-user/signal.c b/linux-user/signal.c
index e11b208..97c3107 100644
--- a/linux-user/signal.c
+++ b/linux-user/signal.c
@@ -4534,9 +4534,7 @@ static void save_user_regs(CPUPPCState *env, struct target_mcontext *frame)
     __put_user(env->lr, &frame->mc_gregs[TARGET_PT_LNK]);
     __put_user(env->xer, &frame->mc_gregs[TARGET_PT_XER]);
 
-    for (i = 0; i < ARRAY_SIZE(env->crf); i++) {
-        ccr |= env->crf[i] << (32 - ((i + 1) * 4));
-    }
+    ccr = ppc_get_cr(env);
     __put_user(ccr, &frame->mc_gregs[TARGET_PT_CCR]);
 
     /* Save Altivec registers if necessary.  */
@@ -4616,9 +4614,7 @@ static void restore_user_regs(CPUPPCState *env,
     __get_user(env->xer, &frame->mc_gregs[TARGET_PT_XER]);
     __get_user(ccr, &frame->mc_gregs[TARGET_PT_CCR]);
 
-    for (i = 0; i < ARRAY_SIZE(env->crf); i++) {
-        env->crf[i] = (ccr >> (32 - ((i + 1) * 4))) & 0xf;
-    }
+    ppc_set_cr(env, ccr);
 
     if (!sig) {
         env->gpr[2] = save_r2;
diff --git a/monitor.c b/monitor.c
index ec73dd4..80acf25 100644
--- a/monitor.c
+++ b/monitor.c
@@ -2963,14 +2963,7 @@ static target_long monitor_get_pc (const struct MonitorDef *md, int val)
 static target_long monitor_get_ccr (const struct MonitorDef *md, int val)
 {
     CPUArchState *env = mon_get_cpu();
-    unsigned int u;
-    int i;
-
-    u = 0;
-    for (i = 0; i < 8; i++)
-        u |= env->crf[i] << (32 - (4 * (i + 1)));
-
-    return u;
+    return ppc_get_cr(env);
 }
 
 static target_long monitor_get_msr (const struct MonitorDef *md, int val)
diff --git a/target-ppc/cpu.h b/target-ppc/cpu.h
index c29ce3b..0c0196d 100644
--- a/target-ppc/cpu.h
+++ b/target-ppc/cpu.h
@@ -1197,6 +1197,26 @@ void ppc_tlb_invalidate_one (CPUPPCState *env, target_ulong addr);
 
 void store_fpscr(CPUPPCState *env, uint64_t arg, uint32_t mask);
 
+static inline uint32_t ppc_get_cr(const CPUPPCState *env)
+{
+    uint32_t cr = 0;
+    int i;
+
+    for (i = 0; i < ARRAY_SIZE(env->crf); i++) {
+        cr |= env->crf[i] << (32 - ((i + 1) * 4));
+    }
+    return cr;
+}
+
+static inline void ppc_set_cr(CPUPPCState *env, uint32_t cr)
+{
+    int i;
+
+    for (i = 0; i < ARRAY_SIZE(env->crf); i++) {
+        env->crf[i] = (cr >> (32 - ((i + 1) * 4))) & 0xF;
+    }
+}
+
 static inline uint64_t ppc_dump_gpr(CPUPPCState *env, int gprn)
 {
     uint64_t gprv;
diff --git a/target-ppc/gdbstub.c b/target-ppc/gdbstub.c
index 14675f4..11d138e 100644
--- a/target-ppc/gdbstub.c
+++ b/target-ppc/gdbstub.c
@@ -135,15 +135,8 @@ int ppc_cpu_gdb_read_register(CPUState *cs, uint8_t *mem_buf, int n)
             gdb_get_regl(mem_buf, env->msr);
             break;
         case 66:
-            {
-                uint32_t cr = 0;
-                int i;
-                for (i = 0; i < 8; i++) {
-                    cr |= env->crf[i] << (32 - ((i + 1) * 4));
-                }
-                gdb_get_reg32(mem_buf, cr);
-                break;
-            }
+            gdb_get_reg32(mem_buf, ppc_get_cr(env));
+            break;
         case 67:
             gdb_get_regl(mem_buf, env->lr);
             break;
@@ -191,15 +184,8 @@ int ppc_cpu_gdb_read_register_apple(CPUState *cs, uint8_t *mem_buf, int n)
             gdb_get_reg64(mem_buf, env->msr);
             break;
         case 66 + 32:
-            {
-                uint32_t cr = 0;
-                int i;
-                for (i = 0; i < 8; i++) {
-                    cr |= env->crf[i] << (32 - ((i + 1) * 4));
-                }
-                gdb_get_reg32(mem_buf, cr);
-                break;
-            }
+            gdb_get_reg32(mem_buf, ppc_get_cr(env));
+            break;
         case 67 + 32:
             gdb_get_reg64(mem_buf, env->lr);
             break;
@@ -243,14 +229,8 @@ int ppc_cpu_gdb_write_register(CPUState *cs, uint8_t *mem_buf, int n)
             ppc_store_msr(env, ldtul_p(mem_buf));
             break;
         case 66:
-            {
-                uint32_t cr = ldl_p(mem_buf);
-                int i;
-                for (i = 0; i < 8; i++) {
-                    env->crf[i] = (cr >> (32 - ((i + 1) * 4))) & 0xF;
-                }
-                break;
-            }
+            ppc_set_cr(env, ldl_p(mem_buf));
+            break;
         case 67:
             env->lr = ldtul_p(mem_buf);
             break;
@@ -293,14 +273,8 @@ int ppc_cpu_gdb_write_register_apple(CPUState *cs, uint8_t *mem_buf, int n)
             ppc_store_msr(env, ldq_p(mem_buf));
             break;
         case 66 + 32:
-            {
-                uint32_t cr = ldl_p(mem_buf);
-                int i;
-                for (i = 0; i < 8; i++) {
-                    env->crf[i] = (cr >> (32 - ((i + 1) * 4))) & 0xF;
-                }
-                break;
-            }
+            ppc_set_cr(env, ldl_p(mem_buf));
+            break;
         case 67 + 32:
             env->lr = ldq_p(mem_buf);
             break;
diff --git a/target-ppc/kvm.c b/target-ppc/kvm.c
index 9c23c6b..e541b9e 100644
--- a/target-ppc/kvm.c
+++ b/target-ppc/kvm.c
@@ -831,10 +831,7 @@ int kvm_arch_put_registers(CPUState *cs, int level)
     for (i = 0;i < 32; i++)
         regs.gpr[i] = env->gpr[i];
 
-    regs.cr = 0;
-    for (i = 0; i < 8; i++) {
-        regs.cr |= (env->crf[i] & 15) << (4 * (7 - i));
-    }
+    regs.cr = ppc_get_cr(env);
 
     ret = kvm_vcpu_ioctl(cs, KVM_SET_REGS, &regs);
     if (ret < 0)
@@ -955,11 +952,7 @@ int kvm_arch_get_registers(CPUState *cs)
     if (ret < 0)
         return ret;
 
-    cr = regs.cr;
-    for (i = 7; i >= 0; i--) {
-        env->crf[i] = cr & 15;
-        cr >>= 4;
-    }
+    ppc_set_cr(env, regs.cr);
 
     env->ctr = regs.ctr;
     env->lr = regs.lr;
-- 
1.8.3.1

  parent reply	other threads:[~2014-09-15 15:04 UTC|newest]

Thread overview: 44+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2014-09-15 15:03 [Qemu-devel] [PATCH v2 00/14] TCG ppc speedups Paolo Bonzini
2014-09-15 15:03 ` [Qemu-devel] [PATCH 01/14] ppc: do not look at the MMU index to detect PR/HV mode Paolo Bonzini
2014-09-15 15:03 ` [Qemu-devel] [PATCH 02/14] softmmu: support up to 12 MMU modes Paolo Bonzini
2014-09-15 15:03 ` [Qemu-devel] [PATCH 03/14] target-ppc: use separate indices for various translation modes Paolo Bonzini
2014-09-16 17:20   ` Tom Musta
2014-09-16 18:02     ` Richard Henderson
2014-09-16 18:27       ` Paolo Bonzini
2014-09-16 18:41         ` Richard Henderson
2014-09-16 22:23           ` Richard Henderson
2014-09-17  6:22             ` Paolo Bonzini
2014-09-17  8:53               ` Paolo Bonzini
2014-09-17 15:33                 ` Richard Henderson
2014-09-17 15:50                   ` Paolo Bonzini
2014-09-17 15:55                     ` Richard Henderson
2014-09-16 18:49     ` Peter Maydell
2014-09-16 22:13       ` Richard Henderson
2014-09-15 15:03 ` Paolo Bonzini [this message]
2014-09-18 19:24   ` [Qemu-devel] [PATCH 04/14] ppc: introduce ppc_get_cr and ppc_set_cr Tom Musta
2014-09-15 15:03 ` [Qemu-devel] [PATCH 05/14] ppc: use CRF_* in fpu_helper.c Paolo Bonzini
2014-09-15 15:03 ` [Qemu-devel] [PATCH 06/14] ppc: introduce helpers for mfocrf/mtocrf Paolo Bonzini
2014-09-18 19:32   ` Tom Musta
2014-09-18 21:01   ` Richard Henderson
2014-09-15 15:03 ` [Qemu-devel] [PATCH 07/14] ppc: reorganize gen_compute_fprf Paolo Bonzini
2014-09-18 19:48   ` Tom Musta
2014-09-15 15:03 ` [Qemu-devel] [PATCH 08/14] ppc: introduce gen_op_mfcr/gen_op_mtcr Paolo Bonzini
2014-09-18 19:49   ` Tom Musta
2014-09-18 21:38   ` Richard Henderson
2014-09-19 13:31     ` Paolo Bonzini
2014-09-15 15:03 ` [Qemu-devel] [PATCH 09/14] ppc: introduce ppc_get_crf and ppc_set_crf Paolo Bonzini
2014-09-18 19:51   ` Tom Musta
2014-09-19 14:52     ` Paolo Bonzini
2014-09-15 15:03 ` [Qemu-devel] [PATCH 10/14] ppc: use movcond for isel Paolo Bonzini
2014-09-18 20:05   ` Tom Musta
2014-09-15 15:03 ` [Qemu-devel] [PATCH 11/14] ppc: store CR registers in 32 1-bit registers Paolo Bonzini
2014-09-18 20:25   ` Tom Musta
2014-09-19 13:53     ` Paolo Bonzini
2014-09-15 15:03 ` [Qemu-devel] [PATCH 12/14] ppc: use movcond to implement evsel Paolo Bonzini
2014-09-15 15:03 ` [Qemu-devel] [PATCH 13/14] ppc: inline ppc_set_crf when clearer Paolo Bonzini
2014-09-18 20:33   ` Tom Musta
2014-09-19 13:51     ` Paolo Bonzini
2014-09-15 15:03 ` [Qemu-devel] [PATCH 14/14] ppc: dump all 32 CR bits Paolo Bonzini
2014-09-18 20:43 ` [Qemu-devel] [PATCH v2 00/14] TCG ppc speedups Tom Musta
2014-09-19 15:16   ` Paolo Bonzini
2014-11-03 11:56 ` Alexander Graf

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