From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:52450) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1XTXp8-0008KL-IY for qemu-devel@nongnu.org; Mon, 15 Sep 2014 11:04:23 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1XTXoz-0007r4-A2 for qemu-devel@nongnu.org; Mon, 15 Sep 2014 11:04:14 -0400 Received: from mail-we0-x230.google.com ([2a00:1450:400c:c03::230]:52393) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1XTXoy-0007p9-WF for qemu-devel@nongnu.org; Mon, 15 Sep 2014 11:04:05 -0400 Received: by mail-we0-f176.google.com with SMTP id q58so4134235wes.7 for ; Mon, 15 Sep 2014 08:04:04 -0700 (PDT) Sender: Paolo Bonzini From: Paolo Bonzini Date: Mon, 15 Sep 2014 17:03:35 +0200 Message-Id: <1410793421-6453-9-git-send-email-pbonzini@redhat.com> In-Reply-To: <1410793421-6453-1-git-send-email-pbonzini@redhat.com> References: <1410793421-6453-1-git-send-email-pbonzini@redhat.com> Subject: [Qemu-devel] [PATCH 08/14] ppc: introduce gen_op_mfcr/gen_op_mtcr List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org Cc: tommusta@gmail.com, agraf@suse.de Signed-off-by: Paolo Bonzini --- v1->v2: fixed TCG debug failures target-ppc/translate.c | 61 +++++++++++++++++++++++++++++++++++--------------- 1 file changed, 43 insertions(+), 18 deletions(-) diff --git a/target-ppc/translate.c b/target-ppc/translate.c index a8b6b7c..52062a8 100644 --- a/target-ppc/translate.c +++ b/target-ppc/translate.c @@ -250,6 +250,21 @@ static inline void gen_reset_fpstatus(void) gen_helper_reset_fpstatus(cpu_env); } +static inline void gen_op_mfcr(TCGv_i32 dest, int first_cr, int shift) +{ + tcg_gen_shli_i32(dest, cpu_crf[first_cr >> 2], shift); +} + +static inline void gen_op_mtcr(int first_cr, TCGv_i32 src, int shift) +{ + if (shift) { + tcg_gen_shri_i32(cpu_crf[first_cr >> 2], src, shift); + tcg_gen_andi_i32(cpu_crf[first_cr >> 2], cpu_crf[first_cr >> 2], 0x0F); + } else { + tcg_gen_andi_i32(cpu_crf[first_cr >> 2], src, 0x0F); + } +} + static inline void gen_compute_fprf(TCGv_i64 arg, int set_fprf, int set_rc) { TCGv_i32 t0; @@ -262,7 +277,7 @@ static inline void gen_compute_fprf(TCGv_i64 arg, int set_fprf, int set_rc) tcg_gen_movi_i32(t0, set_fprf != 0); gen_helper_compute_fprf(t0, cpu_env, arg, t0); if (set_rc) { - tcg_gen_mov_i32(cpu_crf[1], t0); + gen_op_mtcr(4, t0, 0); } if (set_fprf != 0) { @@ -2457,6 +2472,7 @@ static void gen_fmrgow(DisasContext *ctx) static void gen_mcrfs(DisasContext *ctx) { TCGv tmp = tcg_temp_new(); + TCGv_i32 tmp32 = tcg_temp_new_i32(); int bfa; if (unlikely(!ctx->fpu_enabled)) { @@ -2465,10 +2481,11 @@ static void gen_mcrfs(DisasContext *ctx) } bfa = 4 * (7 - crfS(ctx->opcode)); tcg_gen_shri_tl(tmp, cpu_fpscr, bfa); - tcg_gen_trunc_tl_i32(cpu_crf[crfD(ctx->opcode)], tmp); + tcg_gen_trunc_tl_i32(tmp32, tmp); tcg_temp_free(tmp); - tcg_gen_andi_i32(cpu_crf[crfD(ctx->opcode)], cpu_crf[crfD(ctx->opcode)], 0xf); + gen_op_mtcr(crfD(ctx->opcode) << 2, tmp32, 0); tcg_gen_andi_tl(cpu_fpscr, cpu_fpscr, ~(0xF << bfa)); + tcg_temp_free_i32(tmp32); } /* mffs */ @@ -2503,8 +2520,10 @@ static void gen_mtfsb0(DisasContext *ctx) tcg_temp_free_i32(t0); } if (unlikely(Rc(ctx->opcode) != 0)) { - tcg_gen_trunc_tl_i32(cpu_crf[1], cpu_fpscr); - tcg_gen_shri_i32(cpu_crf[1], cpu_crf[1], FPSCR_OX); + TCGv_i32 tmp32 = tcg_temp_new_i32(); + tcg_gen_trunc_tl_i32(tmp32, cpu_fpscr); + gen_op_mtcr(4, tmp32, FPSCR_OX); + tcg_temp_free_i32(tmp32); } } @@ -2529,8 +2548,10 @@ static void gen_mtfsb1(DisasContext *ctx) tcg_temp_free_i32(t0); } if (unlikely(Rc(ctx->opcode) != 0)) { - tcg_gen_trunc_tl_i32(cpu_crf[1], cpu_fpscr); - tcg_gen_shri_i32(cpu_crf[1], cpu_crf[1], FPSCR_OX); + TCGv_i32 tmp32 = tcg_temp_new_i32(); + tcg_gen_trunc_tl_i32(tmp32, cpu_fpscr); + gen_op_mtcr(4, tmp32, FPSCR_OX); + tcg_temp_free_i32(tmp32); } /* We can raise a differed exception */ gen_helper_float_check_status(cpu_env); @@ -2564,8 +2585,10 @@ static void gen_mtfsf(DisasContext *ctx) gen_helper_store_fpscr(cpu_env, cpu_fpr[rB(ctx->opcode)], t0); tcg_temp_free_i32(t0); if (unlikely(Rc(ctx->opcode) != 0)) { - tcg_gen_trunc_tl_i32(cpu_crf[1], cpu_fpscr); - tcg_gen_shri_i32(cpu_crf[1], cpu_crf[1], FPSCR_OX); + TCGv_i32 tmp32 = tcg_temp_new_i32(); + tcg_gen_trunc_tl_i32(tmp32, cpu_fpscr); + gen_op_mtcr(4, tmp32, FPSCR_OX); + tcg_temp_free_i32(tmp32); } /* We can raise a differed exception */ gen_helper_float_check_status(cpu_env); @@ -2598,8 +2621,10 @@ static void gen_mtfsfi(DisasContext *ctx) tcg_temp_free_i64(t0); tcg_temp_free_i32(t1); if (unlikely(Rc(ctx->opcode) != 0)) { - tcg_gen_trunc_tl_i32(cpu_crf[1], cpu_fpscr); - tcg_gen_shri_i32(cpu_crf[1], cpu_crf[1], FPSCR_OX); + TCGv_i32 tmp32 = tcg_temp_new_i32(); + tcg_gen_trunc_tl_i32(tmp32, cpu_fpscr); + gen_op_mtcr(4, tmp32, FPSCR_OX); + tcg_temp_free_i32(tmp32); } /* We can raise a differed exception */ gen_helper_float_check_status(cpu_env); @@ -4166,10 +4191,11 @@ static void gen_mfcr(DisasContext *ctx) if (likely(ctx->opcode & 0x00100000)) { crm = CRM(ctx->opcode); if (likely(crm && ((crm & (crm - 1)) == 0))) { + TCGv_i32 t0 = tcg_temp_new_i32(); crn = ctz32 (crm); - tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], cpu_crf[7 - crn]); - tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)], - cpu_gpr[rD(ctx->opcode)], crn * 4); + gen_op_mfcr(t0, (7 - crn) * 4, crn * 4); + tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], t0); + tcg_temp_free_i32(t0); } } else { gen_helper_mfocrf(cpu_gpr[rD(ctx->opcode)], cpu_env); @@ -4262,8 +4288,7 @@ static void gen_mtcrf(DisasContext *ctx) TCGv_i32 temp = tcg_temp_new_i32(); crn = ctz32 (crm); tcg_gen_trunc_tl_i32(temp, cpu_gpr[rS(ctx->opcode)]); - tcg_gen_shri_i32(temp, temp, crn * 4); - tcg_gen_andi_i32(cpu_crf[7 - crn], temp, 0xf); + gen_op_mtcr((7 - crn) * 4, temp, crn * 4); tcg_temp_free_i32(temp); } } else { @@ -8188,13 +8213,13 @@ static void gen_set_cr1_from_fpscr(DisasContext *ctx) { TCGv_i32 tmp = tcg_temp_new_i32(); tcg_gen_trunc_tl_i32(tmp, cpu_fpscr); - tcg_gen_shri_i32(cpu_crf[1], tmp, 28); + gen_op_mtcr(4, tmp, 28); tcg_temp_free_i32(tmp); } #else static void gen_set_cr1_from_fpscr(DisasContext *ctx) { - tcg_gen_shri_tl(cpu_crf[1], cpu_fpscr, 28); + gen_op_mtcr(4, cpu_fpscr, 28); } #endif -- 1.8.3.1