From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:47786) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1XW22i-00079W-CA for qemu-devel@nongnu.org; Mon, 22 Sep 2014 07:44:38 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1XW22c-0008CC-1Y for qemu-devel@nongnu.org; Mon, 22 Sep 2014 07:44:32 -0400 Received: from mx1.redhat.com ([209.132.183.28]:32253) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1XW22b-0008AA-PA for qemu-devel@nongnu.org; Mon, 22 Sep 2014 07:44:25 -0400 From: Stefan Hajnoczi Date: Mon, 22 Sep 2014 12:42:17 +0100 Message-Id: <1411386150-24003-47-git-send-email-stefanha@redhat.com> In-Reply-To: <1411386150-24003-1-git-send-email-stefanha@redhat.com> References: <1411386150-24003-1-git-send-email-stefanha@redhat.com> Subject: [Qemu-devel] [PULL v2 46/59] ahci: MSI capability should be at 0x80, not 0x50. List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org Cc: Peter Maydell , John Snow , Stefan Hajnoczi From: John Snow In the Intel ICH9 data sheet, the MSI capability offset in the PCI configuration space for ICH9 AHCI devices is specified to be 0x80. Further, the PCI capability pointer should always point to 0x80 in ICH9 devices, despite the fact that AHCI 1.3 specifies that it should be pointing to PMCAP (Which in this instance would be 0x70) to maintain adherence to the Intel data sheet specifications and real observed behavior. Signed-off-by: John Snow Message-id: 1408643079-30675-3-git-send-email-jsnow@redhat.com Signed-off-by: Stefan Hajnoczi --- hw/ide/ich.c | 7 ++++++- 1 file changed, 6 insertions(+), 1 deletion(-) diff --git a/hw/ide/ich.c b/hw/ide/ich.c index a2f1639..8eb77a1 100644 --- a/hw/ide/ich.c +++ b/hw/ide/ich.c @@ -71,6 +71,7 @@ #include #include +#define ICH9_MSI_CAP_OFFSET 0x80 #define ICH9_SATA_CAP_OFFSET 0xA8 #define ICH9_IDP_BAR 4 @@ -115,7 +116,6 @@ static int pci_ich9_ahci_init(PCIDevice *dev) /* XXX Software should program this register */ dev->config[0x90] = 1 << 6; /* Address Map Register - AHCI mode */ - msi_init(dev, 0x50, 1, true, false); d->ahci.irq = pci_allocate_irq(dev); pci_register_bar(dev, ICH9_IDP_BAR, PCI_BASE_ADDRESS_SPACE_IO, @@ -135,6 +135,11 @@ static int pci_ich9_ahci_init(PCIDevice *dev) (ICH9_IDP_BAR + 0x4) | (ICH9_IDP_INDEX_LOG2 << 4)); d->ahci.idp_offset = ICH9_IDP_INDEX; + /* Although the AHCI 1.3 specification states that the first capability + * should be PMCAP, the Intel ICH9 data sheet specifies that the ICH9 + * AHCI device puts the MSI capability first, pointing to 0x80. */ + msi_init(dev, ICH9_MSI_CAP_OFFSET, 1, true, false); + return 0; } -- 1.9.3