From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:47844) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1XW22o-0007Jw-6u for qemu-devel@nongnu.org; Mon, 22 Sep 2014 07:44:44 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1XW22g-0008DS-Mf for qemu-devel@nongnu.org; Mon, 22 Sep 2014 07:44:38 -0400 Received: from mx1.redhat.com ([209.132.183.28]:12820) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1XW22g-0008Bv-FV for qemu-devel@nongnu.org; Mon, 22 Sep 2014 07:44:30 -0400 From: Stefan Hajnoczi Date: Mon, 22 Sep 2014 12:42:19 +0100 Message-Id: <1411386150-24003-49-git-send-email-stefanha@redhat.com> In-Reply-To: <1411386150-24003-1-git-send-email-stefanha@redhat.com> References: <1411386150-24003-1-git-send-email-stefanha@redhat.com> Subject: [Qemu-devel] [PULL v2 48/59] ahci: add test_pci_enable to ahci-test. List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org Cc: Peter Maydell , John Snow , Stefan Hajnoczi From: John Snow This adds a test wherein we engage the PCI AHCI device and ensure that the memory region for the HBA functionality is now accessible. Under Q35 environments, additional PCI configuration is performed to ensure that the HBA functionality will become usable. Signed-off-by: John Snow Message-id: 1408643079-30675-5-git-send-email-jsnow@redhat.com Signed-off-by: Stefan Hajnoczi --- tests/ahci-test.c | 53 +++++++++++++++++++++++++++++++++++++++++++++++++++++ tests/libqos/pci.c | 6 ++++++ 2 files changed, 59 insertions(+) diff --git a/tests/ahci-test.c b/tests/ahci-test.c index 0674d5e..ee41b41 100644 --- a/tests/ahci-test.c +++ b/tests/ahci-test.c @@ -66,6 +66,7 @@ static uint32_t ahci_fingerprint; /*** Function Declarations ***/ static QPCIDevice *get_ahci_device(void); +static QPCIDevice *start_ahci_device(QPCIDevice *dev, void **hba_base); static void free_ahci_device(QPCIDevice *dev); static void ahci_test_pci_spec(QPCIDevice *ahci); static void ahci_test_pci_caps(QPCIDevice *ahci, uint16_t header, @@ -169,6 +170,44 @@ static void ahci_shutdown(QPCIDevice *ahci) qtest_shutdown(); } +/*** Logical Device Initialization ***/ + +/** + * Start the PCI device and sanity-check default operation. + */ +static void ahci_pci_enable(QPCIDevice *ahci, void **hba_base) +{ + uint8_t reg; + + start_ahci_device(ahci, hba_base); + + switch (ahci_fingerprint) { + case AHCI_INTEL_ICH9: + /* ICH9 has a register at PCI 0x92 that + * acts as a master port enabler mask. */ + reg = qpci_config_readb(ahci, 0x92); + reg |= 0x3F; + qpci_config_writeb(ahci, 0x92, reg); + ASSERT_BIT_SET(qpci_config_readb(ahci, 0x92), 0x3F); + break; + } + +} + +/** + * Map BAR5/ABAR, and engage the PCI device. + */ +static QPCIDevice *start_ahci_device(QPCIDevice *ahci, void **hba_base) +{ + /* Map AHCI's ABAR (BAR5) */ + *hba_base = qpci_iomap(ahci, 5, NULL); + + /* turns on pci.cmd.iose, pci.cmd.mse and pci.cmd.bme */ + qpci_device_enable(ahci); + + return ahci; +} + /*** Specification Adherence Tests ***/ /** @@ -428,6 +467,19 @@ static void test_pci_spec(void) ahci_shutdown(ahci); } +/** + * Engage the PCI AHCI device and sanity check the response. + * Perform additional PCI config space bringup for the HBA. + */ +static void test_pci_enable(void) +{ + QPCIDevice *ahci; + void *hba_base; + ahci = ahci_boot(); + ahci_pci_enable(ahci, &hba_base); + ahci_shutdown(ahci); +} + /******************************************************************************/ int main(int argc, char **argv) @@ -479,6 +531,7 @@ int main(int argc, char **argv) /* Run the tests */ qtest_add_func("/ahci/sanity", test_sanity); qtest_add_func("/ahci/pci_spec", test_pci_spec); + qtest_add_func("/ahci/pci_enable", test_pci_enable); ret = g_test_run(); diff --git a/tests/libqos/pci.c b/tests/libqos/pci.c index d5ce683..4e630c2 100644 --- a/tests/libqos/pci.c +++ b/tests/libqos/pci.c @@ -71,6 +71,12 @@ void qpci_device_enable(QPCIDevice *dev) cmd = qpci_config_readw(dev, PCI_COMMAND); cmd |= PCI_COMMAND_IO | PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER; qpci_config_writew(dev, PCI_COMMAND, cmd); + + /* Verify the bits are now set. */ + cmd = qpci_config_readw(dev, PCI_COMMAND); + g_assert_cmphex(cmd & PCI_COMMAND_IO, ==, PCI_COMMAND_IO); + g_assert_cmphex(cmd & PCI_COMMAND_MEMORY, ==, PCI_COMMAND_MEMORY); + g_assert_cmphex(cmd & PCI_COMMAND_MASTER, ==, PCI_COMMAND_MASTER); } uint8_t qpci_find_capability(QPCIDevice *dev, uint8_t id) -- 1.9.3