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From: "Edgar E. Iglesias" <edgar.iglesias@gmail.com>
To: qemu-devel@nongnu.org, peter.maydell@linaro.org
Cc: rob.herring@linaro.org, peter.crosthwaite@xilinx.com,
	aggelerf@ethz.ch, serge.fdrv@gmail.com, agraf@suse.de,
	greg.bellows@linaro.org, pbonzini@redhat.com,
	alex.bennee@linaro.org, christoffer.dall@linaro.org,
	rth@twiddle.net
Subject: [Qemu-devel] [PATCH v7 04/11] target-arm: Break out exception masking to a separate func
Date: Fri, 26 Sep 2014 18:08:27 +1000	[thread overview]
Message-ID: <1411718914-6608-5-git-send-email-edgar.iglesias@gmail.com> (raw)
In-Reply-To: <1411718914-6608-1-git-send-email-edgar.iglesias@gmail.com>

From: "Edgar E. Iglesias" <edgar.iglesias@xilinx.com>

Reviewed-by: Greg Bellows <greg.bellows@linaro.org>
Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
---
 cpu-exec.c       |  5 ++---
 target-arm/cpu.h | 15 +++++++++++++++
 2 files changed, 17 insertions(+), 3 deletions(-)

diff --git a/cpu-exec.c b/cpu-exec.c
index bd93165..d017588 100644
--- a/cpu-exec.c
+++ b/cpu-exec.c
@@ -596,7 +596,7 @@ int cpu_exec(CPUArchState *env)
                     }
 #elif defined(TARGET_ARM)
                     if (interrupt_request & CPU_INTERRUPT_FIQ
-                        && !(env->daif & PSTATE_F)) {
+                        && arm_excp_unmasked(cpu, EXCP_FIQ)) {
                         cpu->exception_index = EXCP_FIQ;
                         cc->do_interrupt(cpu);
                         next_tb = 0;
@@ -611,8 +611,7 @@ int cpu_exec(CPUArchState *env)
                        We avoid this by disabling interrupts when
                        pc contains a magic address.  */
                     if (interrupt_request & CPU_INTERRUPT_HARD
-                        && !(env->daif & PSTATE_I)
-                        && (!IS_M(env) || env->regs[15] < 0xfffffff0)) {
+                        && arm_excp_unmasked(cpu, EXCP_IRQ)) {
                         cpu->exception_index = EXCP_IRQ;
                         cc->do_interrupt(cpu);
                         next_tb = 0;
diff --git a/target-arm/cpu.h b/target-arm/cpu.h
index e2474d0..a5e8e0d 100644
--- a/target-arm/cpu.h
+++ b/target-arm/cpu.h
@@ -1171,6 +1171,21 @@ bool write_cpustate_to_list(ARMCPU *cpu);
 #  define TARGET_VIRT_ADDR_SPACE_BITS 32
 #endif
 
+static inline bool arm_excp_unmasked(CPUState *cs, unsigned int excp_idx)
+{
+    CPUARMState *env = cs->env_ptr;
+
+    switch (excp_idx) {
+    case EXCP_FIQ:
+        return !(env->daif & PSTATE_F);
+    case EXCP_IRQ:
+        return !(env->daif & PSTATE_I)
+               && (!IS_M(env) || env->regs[15] < 0xfffffff0);
+    default:
+        g_assert_not_reached();
+    }
+}
+
 static inline CPUARMState *cpu_init(const char *cpu_model)
 {
     ARMCPU *cpu = cpu_arm_init(cpu_model);
-- 
1.9.1

  parent reply	other threads:[~2014-09-26  8:15 UTC|newest]

Thread overview: 18+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2014-09-26  8:08 [Qemu-devel] [PATCH v7 00/11] target-arm: Parts of the AArch64 EL2/3 exception model Edgar E. Iglesias
2014-09-26  8:08 ` [Qemu-devel] [PATCH v7 01/11] target-arm: Add HCR_EL2 Edgar E. Iglesias
2014-09-26  8:08 ` [Qemu-devel] [PATCH v7 02/11] target-arm: Add SCR_EL3 Edgar E. Iglesias
2014-09-26 14:46   ` Peter Maydell
2014-09-26 19:45     ` Edgar E. Iglesias
2014-09-26  8:08 ` [Qemu-devel] [PATCH v7 03/11] target-arm: A64: Refactor aarch64_cpu_do_interrupt Edgar E. Iglesias
2014-09-26  8:08 ` Edgar E. Iglesias [this message]
2014-09-26  8:08 ` [Qemu-devel] [PATCH v7 05/11] target-arm: Don't take interrupts targeting lower ELs Edgar E. Iglesias
2014-09-26  8:08 ` [Qemu-devel] [PATCH v7 06/11] target-arm: A64: Correct updates to FAR and ESR on exceptions Edgar E. Iglesias
2014-09-26  8:08 ` [Qemu-devel] [PATCH v7 07/11] target-arm: A64: Emulate the HVC insn Edgar E. Iglesias
2014-09-26  8:08 ` [Qemu-devel] [PATCH v7 08/11] target-arm: Add a Hypervisor Trap exception type Edgar E. Iglesias
2014-09-26  8:08 ` [Qemu-devel] [PATCH v7 09/11] target-arm: A64: Emulate the SMC insn Edgar E. Iglesias
2014-09-26  8:08 ` [Qemu-devel] [PATCH v7 10/11] target-arm: Add IRQ and FIQ routing to EL2 and 3 Edgar E. Iglesias
2014-09-26  8:08 ` [Qemu-devel] [PATCH v7 11/11] target-arm: Add support for VIRQ and VFIQ Edgar E. Iglesias
2014-09-26 15:23 ` [Qemu-devel] [PATCH v7 00/11] target-arm: Parts of the AArch64 EL2/3 exception model Peter Maydell
2014-09-29 10:31   ` Jan Kiszka
2014-09-29 10:41     ` Peter Maydell
2014-09-29 10:48       ` Jan Kiszka

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