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From: Peter Maydell <peter.maydell@linaro.org>
To: qemu-devel@nongnu.org
Subject: [Qemu-devel] [PULL 16/19] target-arm: Add a Hypervisor Trap exception type
Date: Mon, 29 Sep 2014 19:26:50 +0100	[thread overview]
Message-ID: <1412015213-22268-17-git-send-email-peter.maydell@linaro.org> (raw)
In-Reply-To: <1412015213-22268-1-git-send-email-peter.maydell@linaro.org>

From: "Edgar E. Iglesias" <edgar.iglesias@xilinx.com>

Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
Message-id: 1411718914-6608-9-git-send-email-edgar.iglesias@gmail.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 target-arm/cpu.h        | 1 +
 target-arm/helper-a64.c | 1 +
 target-arm/helper.c     | 1 +
 target-arm/internals.h  | 1 +
 4 files changed, 4 insertions(+)

diff --git a/target-arm/cpu.h b/target-arm/cpu.h
index e13b6d4..98610f0 100644
--- a/target-arm/cpu.h
+++ b/target-arm/cpu.h
@@ -52,6 +52,7 @@
 #define EXCP_KERNEL_TRAP     9   /* Jumped to kernel code page.  */
 #define EXCP_STREX          10
 #define EXCP_HVC            11   /* HyperVisor Call */
+#define EXCP_HYP_TRAP       12
 
 #define ARMV7M_EXCP_RESET   1
 #define ARMV7M_EXCP_NMI     2
diff --git a/target-arm/helper-a64.c b/target-arm/helper-a64.c
index 4e6ca26..0a7c155 100644
--- a/target-arm/helper-a64.c
+++ b/target-arm/helper-a64.c
@@ -477,6 +477,7 @@ void aarch64_cpu_do_interrupt(CPUState *cs)
     case EXCP_UDEF:
     case EXCP_SWI:
     case EXCP_HVC:
+    case EXCP_HYP_TRAP:
         env->cp15.esr_el[new_el] = env->exception.syndrome;
         break;
     case EXCP_IRQ:
diff --git a/target-arm/helper.c b/target-arm/helper.c
index 4d5a653..48f549a 100644
--- a/target-arm/helper.c
+++ b/target-arm/helper.c
@@ -3781,6 +3781,7 @@ unsigned int arm_excp_target_el(CPUState *cs, unsigned int excp_idx)
 
     switch (excp_idx) {
     case EXCP_HVC:
+    case EXCP_HYP_TRAP:
         target_el = 2;
         break;
     default:
diff --git a/target-arm/internals.h b/target-arm/internals.h
index 25c5ec3..203c423 100644
--- a/target-arm/internals.h
+++ b/target-arm/internals.h
@@ -54,6 +54,7 @@ static const char * const excnames[] = {
     [EXCP_KERNEL_TRAP] = "QEMU intercept of kernel commpage",
     [EXCP_STREX] = "QEMU intercept of STREX",
     [EXCP_HVC] = "Hypervisor Call",
+    [EXCP_HYP_TRAP] = "Hypervisor Trap",
 };
 
 static inline void arm_log_exception(int idx)
-- 
1.9.1

  parent reply	other threads:[~2014-09-29 18:27 UTC|newest]

Thread overview: 21+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2014-09-29 18:26 [Qemu-devel] [PULL 00/19] target-arm queue Peter Maydell
2014-09-29 18:26 ` [Qemu-devel] [PULL 01/19] target-arm: Implement setting guest breakpoints Peter Maydell
2014-09-29 18:26 ` [Qemu-devel] [PULL 02/19] target-arm: Implement handling of breakpoint firing Peter Maydell
2014-09-29 18:26 ` [Qemu-devel] [PULL 03/19] configure: Build GDB XML for 32 bit ARM CPUs into qemu aarch64 binaries Peter Maydell
2014-09-29 18:26 ` [Qemu-devel] [PULL 04/19] hw/display/blizzard.c: Delete unused function blizzard_rgb2yuv Peter Maydell
2014-09-29 18:26 ` [Qemu-devel] [PULL 05/19] hw/intc/imx_avic.c: Remove unused function imx_avic_set_prio() Peter Maydell
2014-09-29 18:26 ` [Qemu-devel] [PULL 06/19] hw/display/pxa2xx_lcd.c: Remove unused function pxa2xx_dma_rdst_set Peter Maydell
2014-09-29 18:26 ` [Qemu-devel] [PULL 07/19] hw/input/tsc210x.c: Delete unused array tsc2101_rates Peter Maydell
2014-09-29 18:26 ` [Qemu-devel] [PULL 08/19] target-arm: Don't handle c15_cpar changes via tb_flush() Peter Maydell
2014-09-29 18:26 ` [Qemu-devel] [PULL 09/19] target-arm: Add HCR_EL2 Peter Maydell
2014-09-29 18:26 ` [Qemu-devel] [PULL 10/19] target-arm: Add SCR_EL3 Peter Maydell
2014-09-29 18:26 ` [Qemu-devel] [PULL 11/19] target-arm: A64: Refactor aarch64_cpu_do_interrupt Peter Maydell
2014-09-29 18:26 ` [Qemu-devel] [PULL 12/19] target-arm: Break out exception masking to a separate func Peter Maydell
2014-09-29 18:26 ` [Qemu-devel] [PULL 13/19] target-arm: Don't take interrupts targeting lower ELs Peter Maydell
2014-09-29 18:26 ` [Qemu-devel] [PULL 14/19] target-arm: A64: Correct updates to FAR and ESR on exceptions Peter Maydell
2014-09-29 18:26 ` [Qemu-devel] [PULL 15/19] target-arm: A64: Emulate the HVC insn Peter Maydell
2014-09-29 18:26 ` Peter Maydell [this message]
2014-09-29 18:26 ` [Qemu-devel] [PULL 17/19] target-arm: A64: Emulate the SMC insn Peter Maydell
2014-09-29 18:26 ` [Qemu-devel] [PULL 18/19] target-arm: Add IRQ and FIQ routing to EL2 and 3 Peter Maydell
2014-09-29 18:26 ` [Qemu-devel] [PULL 19/19] target-arm: Add support for VIRQ and VFIQ Peter Maydell
2014-09-30 10:52 ` [Qemu-devel] [PULL 00/19] target-arm queue Peter Maydell

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