From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:40891) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1XYffA-0008DE-4v for qemu-devel@nongnu.org; Mon, 29 Sep 2014 14:27:09 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1XYff8-0007VK-N4 for qemu-devel@nongnu.org; Mon, 29 Sep 2014 14:27:08 -0400 Received: from mnementh.archaic.org.uk ([2001:8b0:1d0::1]:54082) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1XYff8-0007L2-Gi for qemu-devel@nongnu.org; Mon, 29 Sep 2014 14:27:06 -0400 Received: from pm215 by mnementh.archaic.org.uk with local (Exim 4.80) (envelope-from ) id 1XYfew-0005p4-Mp for qemu-devel@nongnu.org; Mon, 29 Sep 2014 19:26:54 +0100 From: Peter Maydell Date: Mon, 29 Sep 2014 19:26:52 +0100 Message-Id: <1412015213-22268-19-git-send-email-peter.maydell@linaro.org> In-Reply-To: <1412015213-22268-1-git-send-email-peter.maydell@linaro.org> References: <1412015213-22268-1-git-send-email-peter.maydell@linaro.org> Subject: [Qemu-devel] [PULL 18/19] target-arm: Add IRQ and FIQ routing to EL2 and 3 List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org From: "Edgar E. Iglesias" Reviewed-by: Greg Bellows Signed-off-by: Edgar E. Iglesias Message-id: 1411718914-6608-11-git-send-email-edgar.iglesias@gmail.com Signed-off-by: Peter Maydell --- target-arm/cpu.h | 10 ++++++++++ target-arm/helper.c | 17 +++++++++++++++++ 2 files changed, 27 insertions(+) diff --git a/target-arm/cpu.h b/target-arm/cpu.h index d104a7d..11ba9d6 100644 --- a/target-arm/cpu.h +++ b/target-arm/cpu.h @@ -1180,6 +1180,10 @@ static inline bool arm_excp_unmasked(CPUState *cs, unsigned int excp_idx) CPUARMState *env = cs->env_ptr; unsigned int cur_el = arm_current_pl(env); unsigned int target_el = arm_excp_target_el(cs, excp_idx); + /* FIXME: Use actual secure state. */ + bool secure = false; + /* If in EL1/0, Physical IRQ routing to EL2 only happens from NS state. */ + bool irq_can_hyp = !secure && cur_el < 2 && target_el == 2; /* Don't take exceptions if they target a lower EL. */ if (cur_el > target_el) { @@ -1188,8 +1192,14 @@ static inline bool arm_excp_unmasked(CPUState *cs, unsigned int excp_idx) switch (excp_idx) { case EXCP_FIQ: + if (irq_can_hyp && (env->cp15.hcr_el2 & HCR_FMO)) { + return true; + } return !(env->daif & PSTATE_F); case EXCP_IRQ: + if (irq_can_hyp && (env->cp15.hcr_el2 & HCR_IMO)) { + return true; + } return !(env->daif & PSTATE_I) && (!IS_M(env) || env->regs[15] < 0xfffffff0); default: diff --git a/target-arm/helper.c b/target-arm/helper.c index af2d2e6..6135594 100644 --- a/target-arm/helper.c +++ b/target-arm/helper.c @@ -3773,6 +3773,8 @@ unsigned int arm_excp_target_el(CPUState *cs, unsigned int excp_idx) CPUARMState *env = &cpu->env; unsigned int cur_el = arm_current_pl(env); unsigned int target_el; + /* FIXME: Use actual secure state. */ + bool secure = false; if (!env->aarch64) { /* TODO: Add EL2 and 3 exception handling for AArch32. */ @@ -3787,6 +3789,21 @@ unsigned int arm_excp_target_el(CPUState *cs, unsigned int excp_idx) case EXCP_SMC: target_el = 3; break; + case EXCP_FIQ: + case EXCP_IRQ: + { + const uint64_t hcr_mask = excp_idx == EXCP_FIQ ? HCR_FMO : HCR_IMO; + const uint32_t scr_mask = excp_idx == EXCP_FIQ ? SCR_FIQ : SCR_IRQ; + + target_el = 1; + if (!secure && (env->cp15.hcr_el2 & hcr_mask)) { + target_el = 2; + } + if (env->cp15.scr_el3 & scr_mask) { + target_el = 3; + } + break; + } default: target_el = MAX(cur_el, 1); break; -- 1.9.1