From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:42860) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1XZ5JA-0000I8-2J for qemu-devel@nongnu.org; Tue, 30 Sep 2014 17:50:14 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1XZ5J1-0003Fi-QF for qemu-devel@nongnu.org; Tue, 30 Sep 2014 17:50:07 -0400 Received: from mail-pd0-f170.google.com ([209.85.192.170]:40297) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1XZ5J1-0003AU-Ke for qemu-devel@nongnu.org; Tue, 30 Sep 2014 17:49:59 -0400 Received: by mail-pd0-f170.google.com with SMTP id ft15so4315415pdb.29 for ; Tue, 30 Sep 2014 14:49:54 -0700 (PDT) From: Greg Bellows Date: Tue, 30 Sep 2014 16:49:12 -0500 Message-Id: <1412113785-21525-1-git-send-email-greg.bellows@linaro.org> Subject: [Qemu-devel] [PATCH v5 00/33] target-arm: add Security Extensions for CPUs List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org, peter.maydell@linaro.org, serge.fdrv@gmail.com, edgar.iglesias@gmail.com, aggelerf@ethz.ch Cc: Greg Bellows Version 5 of the ARM processor security extension (TrustZone) support. This patchset includes changes to support the processor security extensions on ARMv7 aarch32 with hooks for later enabling v8 aarch64/32. Summary of changes from v4 -> v5: - Renamed arm_current_pl to arm_current_el - Added banked MAIR support - Added gdb SCR register - Bugfixes and clean-up - Reordered patches so infrastructure happens before use. More detailed change history included on a per-patch basis. Fabian Aggeler (27): target-arm: increase arrays of registers R13 & R14 target-arm: add arm_is_secure() function target-arm: make arm_current_pl() return PL3 target-arm: A32: Emulate the SMC instruction target-arm: extend async excp masking target-arm: add async excp target_el function target-arm: add macros to access banked registers target-arm: arrayfying fieldoffset for banking target-arm: insert Aarch32 cpregs twice into hashtable target-arm: move Aarch32 SCR into security reglist target-arm: implement IRQ/FIQ routing to Monitor mode target-arm: Respect SCR.FW, SCR.AW and SCTLR.NMFI target-arm: add NSACR register target-arm: add MVBAR support target-arm: add SCTLR_EL3 and make SCTLR banked target-arm: make CSSELR banked target-arm: add TTBR0_EL3 and make TTBR0/1 banked target-arm: add TCR_EL3 and make TTBCR banked target-arm: make c2_mask and c2_base_mask banked target-arm: make DACR banked target-arm: make IFSR banked target-arm: make DFSR banked target-arm: make IFAR/DFAR banked target-arm: make PAR banked target-arm: make VBAR banked target-arm: make c13 cp regs banked (FCSEIDR, ...) target-arm: add cpu feature EL3 to CPUs with Security Extensions Greg Bellows (3): target-arm: rename arm_current_pl to arm_current_el target-arm: make MAIR0/1 banked target-arm: add GDB scr register Sergey Fedorov (3): target-arm: reject switching to monitor mode target-arm: add non-secure Translation Block flag target-arm: add SDER definition gdb-xml/arm-core.xml | 1 + hw/arm/pxa2xx.c | 4 +- target-arm/cpu.c | 13 +- target-arm/cpu.h | 471 +++++++++++++++++++++++---- target-arm/gdbstub.c | 3 + target-arm/helper-a64.c | 6 +- target-arm/helper.c | 772 ++++++++++++++++++++++++++++++++++----------- target-arm/internals.h | 11 +- target-arm/machine.c | 4 +- target-arm/op_helper.c | 19 +- target-arm/translate-a64.c | 3 +- target-arm/translate.c | 56 +++- target-arm/translate.h | 1 + 13 files changed, 1092 insertions(+), 272 deletions(-) -- 1.8.3.2