From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:43249) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1XZ5JT-0000jb-ED for qemu-devel@nongnu.org; Tue, 30 Sep 2014 17:50:32 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1XZ5JO-0003uM-Li for qemu-devel@nongnu.org; Tue, 30 Sep 2014 17:50:27 -0400 Received: from mail-pa0-f50.google.com ([209.85.220.50]:49538) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1XZ5JO-0003tO-4h for qemu-devel@nongnu.org; Tue, 30 Sep 2014 17:50:22 -0400 Received: by mail-pa0-f50.google.com with SMTP id kx10so6133282pab.37 for ; Tue, 30 Sep 2014 14:50:20 -0700 (PDT) From: Greg Bellows Date: Tue, 30 Sep 2014 16:49:29 -0500 Message-Id: <1412113785-21525-18-git-send-email-greg.bellows@linaro.org> In-Reply-To: <1412113785-21525-1-git-send-email-greg.bellows@linaro.org> References: <1412113785-21525-1-git-send-email-greg.bellows@linaro.org> Subject: [Qemu-devel] [PATCH v5 17/33] target-arm: add SDER definition List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org, peter.maydell@linaro.org, serge.fdrv@gmail.com, edgar.iglesias@gmail.com, aggelerf@ethz.ch Cc: Sergey Fedorov , Greg Bellows From: Sergey Fedorov Signed-off-by: Sergey Fedorov Signed-off-by: Fabian Aggeler Signed-off-by: Greg Bellows --- target-arm/cpu.h | 1 + target-arm/helper.c | 3 +++ 2 files changed, 4 insertions(+) diff --git a/target-arm/cpu.h b/target-arm/cpu.h index 5be258b..f7148d1 100644 --- a/target-arm/cpu.h +++ b/target-arm/cpu.h @@ -181,6 +181,7 @@ typedef struct CPUARMState { uint64_t c1_sys; /* System control register. */ uint64_t c1_coproc; /* Coprocessor access register. */ uint32_t c1_xscaleauxcr; /* XScale auxiliary control register. */ + uint32_t c1_sder; /* Secure debug enable register. */ uint32_t c1_nsacr; /* Non-secure access control register. */ uint64_t ttbr0_el1; /* MMU translation table base 0. */ uint64_t ttbr1_el1; /* MMU translation table base 1. */ diff --git a/target-arm/helper.c b/target-arm/helper.c index 0c3663a..778c21c 100644 --- a/target-arm/helper.c +++ b/target-arm/helper.c @@ -2409,6 +2409,9 @@ static const ARMCPRegInfo v7_el3_cp_reginfo[] = { { .name = "SCR", .cp = 15, .crn = 1, .crm = 1, .opc1 = 0, .opc2 = 0, .access = PL3_RW, .fieldoffset = offsetof(CPUARMState, cp15.scr_el3), .resetvalue = 0, .writefn = scr_write}, + { .name = "SDER", .cp = 15, .crn = 1, .crm = 1, .opc1 = 0, .opc2 = 1, + .access = PL3_RW, .resetvalue = 0, + .fieldoffset = offsetof(CPUARMState, cp15.c1_sder) }, { .name = "NSACR", .cp = 15, .crn = 1, .crm = 1, .opc1 = 0, .opc2 = 2, .access = PL3_RW | PL1_R, .resetvalue = 0, .writefn = nsacr_write, .readfn = nsacr_read, -- 1.8.3.2