From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:43329) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1XZ5JZ-0000tm-OM for qemu-devel@nongnu.org; Tue, 30 Sep 2014 17:50:39 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1XZ5JU-0003yP-V9 for qemu-devel@nongnu.org; Tue, 30 Sep 2014 17:50:33 -0400 Received: from mail-pd0-f180.google.com ([209.85.192.180]:57841) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1XZ5JT-0003xB-Ms for qemu-devel@nongnu.org; Tue, 30 Sep 2014 17:50:28 -0400 Received: by mail-pd0-f180.google.com with SMTP id fp1so5894259pdb.11 for ; Tue, 30 Sep 2014 14:50:21 -0700 (PDT) From: Greg Bellows Date: Tue, 30 Sep 2014 16:49:30 -0500 Message-Id: <1412113785-21525-19-git-send-email-greg.bellows@linaro.org> In-Reply-To: <1412113785-21525-1-git-send-email-greg.bellows@linaro.org> References: <1412113785-21525-1-git-send-email-greg.bellows@linaro.org> Subject: [Qemu-devel] [PATCH v5 18/33] target-arm: add MVBAR support List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org, peter.maydell@linaro.org, serge.fdrv@gmail.com, edgar.iglesias@gmail.com, aggelerf@ethz.ch Cc: Sergey Fedorov , Greg Bellows From: Fabian Aggeler Use MVBAR register as exception vector base address for exceptions taken to CPU monitor mode. Signed-off-by: Sergey Fedorov Signed-off-by: Fabian Aggeler Signed-off-by: Greg Bellows --- target-arm/cpu.h | 1 + target-arm/helper.c | 15 +++++++++------ 2 files changed, 10 insertions(+), 6 deletions(-) diff --git a/target-arm/cpu.h b/target-arm/cpu.h index f7148d1..1b6ce8a 100644 --- a/target-arm/cpu.h +++ b/target-arm/cpu.h @@ -211,6 +211,7 @@ typedef struct CPUARMState { uint32_t c9_pminten; /* perf monitor interrupt enables */ uint64_t mair_el1; uint64_t vbar_el[4]; /* vector base address register */ + uint64_t mvbar; /* (monitor) vector base address register */ uint32_t c13_fcse; /* FCSE PID. */ uint64_t contextidr_el1; /* Context ID. */ uint64_t tpidr_el0; /* User RW Thread register. */ diff --git a/target-arm/helper.c b/target-arm/helper.c index 778c21c..4ad55d5 100644 --- a/target-arm/helper.c +++ b/target-arm/helper.c @@ -2416,6 +2416,9 @@ static const ARMCPRegInfo v7_el3_cp_reginfo[] = { .access = PL3_RW | PL1_R, .resetvalue = 0, .writefn = nsacr_write, .readfn = nsacr_read, .fieldoffset = offsetof(CPUARMState, cp15.c1_nsacr) }, + { .name = "MVBAR", .cp = 15, .crn = 12, .crm = 0, .opc1 = 0, .opc2 = 1, + .access = PL3_RW, .writefn = vbar_write, .resetvalue = 0, + .fieldoffset = offsetof(CPUARMState, cp15.mvbar) }, REGINFO_SENTINEL }; @@ -4365,16 +4368,16 @@ void arm_cpu_do_interrupt(CPUState *cs) cpu_abort(cs, "Unhandled exception 0x%x\n", cs->exception_index); return; /* Never happens. Keep compiler happy. */ } - /* High vectors. */ - if (env->cp15.c1_sys & SCTLR_V) { - /* when enabled, base address cannot be remapped. */ + + if (new_mode == ARM_CPU_MODE_MON) { + addr += env->cp15.mvbar; + } else if (env->cp15.c1_sys & SCTLR_V) { + /* High vectors. When enabled, base address cannot be remapped. */ addr += 0xffff0000; } else { /* ARM v7 architectures provide a vector base address register to remap * the interrupt vector table. - * This register is only followed in non-monitor mode, and has a secure - * and un-secure copy. Since the cpu is always in a un-secure operation - * and is never in monitor mode this feature is always active. + * This register is only followed in non-monitor mode, and is banked. * Note: only bits 31:5 are valid. */ addr += env->cp15.vbar_el[1]; -- 1.8.3.2