From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:43374) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1XZ5Jh-0000yP-Th for qemu-devel@nongnu.org; Tue, 30 Sep 2014 17:50:47 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1XZ5Jc-00040W-80 for qemu-devel@nongnu.org; Tue, 30 Sep 2014 17:50:41 -0400 Received: from mail-pa0-f48.google.com ([209.85.220.48]:61014) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1XZ5JX-0003zG-Fw for qemu-devel@nongnu.org; Tue, 30 Sep 2014 17:50:36 -0400 Received: by mail-pa0-f48.google.com with SMTP id eu11so2532568pac.7 for ; Tue, 30 Sep 2014 14:50:29 -0700 (PDT) From: Greg Bellows Date: Tue, 30 Sep 2014 16:49:35 -0500 Message-Id: <1412113785-21525-24-git-send-email-greg.bellows@linaro.org> In-Reply-To: <1412113785-21525-1-git-send-email-greg.bellows@linaro.org> References: <1412113785-21525-1-git-send-email-greg.bellows@linaro.org> Subject: [Qemu-devel] [PATCH v5 23/33] target-arm: make c2_mask and c2_base_mask banked List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org, peter.maydell@linaro.org, serge.fdrv@gmail.com, edgar.iglesias@gmail.com, aggelerf@ethz.ch Cc: Greg Bellows From: Fabian Aggeler Since TTBCR is banked we will bank c2_mask and c2_base_mask too. This avoids recalculating them on switches from secure to non-secure world. Signed-off-by: Fabian Aggeler Signed-off-by: Greg Bellows ---------- v4 -> v5 - Changed c2_mask updates to use the TTBCR cpreg bank flag for selcting the secure bank instead of the A32_BANKED_CURRENT macro. This more accurately chooses the correct bank matching that of the TTBCR being accessed. --- target-arm/cpu.h | 10 ++++++++-- target-arm/helper.c | 24 ++++++++++++++++++------ 2 files changed, 26 insertions(+), 8 deletions(-) diff --git a/target-arm/cpu.h b/target-arm/cpu.h index 477c219..54bce55 100644 --- a/target-arm/cpu.h +++ b/target-arm/cpu.h @@ -231,8 +231,14 @@ typedef struct CPUARMState { uint64_t tcr_el3; }; }; - uint32_t c2_mask; /* MMU translation table base selection mask. */ - uint32_t c2_base_mask; /* MMU translation table base 0 mask. */ + struct { /* MMU translation table base selection mask. */ + uint32_t c2_mask_ns; + uint32_t c2_mask_s; + }; + struct { /* MMU translation table base 0 mask. */ + uint32_t c2_base_mask_ns; + uint32_t c2_base_mask_s; + }; uint32_t c2_data; /* MPU data cachable bits. */ uint32_t c2_insn; /* MPU instruction cachable bits. */ uint32_t c3; /* MMU domain access control register diff --git a/target-arm/helper.c b/target-arm/helper.c index bdb76e0..a77ab95 100644 --- a/target-arm/helper.c +++ b/target-arm/helper.c @@ -1597,8 +1597,14 @@ static void vmsa_ttbcr_raw_write(CPUARMState *env, const ARMCPRegInfo *ri, * and the c2_mask and c2_base_mask values are meaningless. */ raw_write(env, ri, value); - env->cp15.c2_mask = ~(((uint32_t)0xffffffffu) >> maskshift); - env->cp15.c2_base_mask = ~((uint32_t)0x3fffu >> maskshift); + + /* Update the masks corresponding to the the TTBCR bank being written */ + A32_BANKED_REG_SET(env, c2_mask, + ((ri->type & ARM_CP_BANK_S) == ARM_CP_BANK_S), + ~(((uint32_t)0xffffffffu) >> maskshift)); + A32_BANKED_REG_SET(env, c2_base_mask, + ((ri->type & ARM_CP_BANK_S) == ARM_CP_BANK_S), + ~((uint32_t)0x3fffu >> maskshift)); } static void vmsa_ttbcr_write(CPUARMState *env, const ARMCPRegInfo *ri, @@ -1617,9 +1623,15 @@ static void vmsa_ttbcr_write(CPUARMState *env, const ARMCPRegInfo *ri, static void vmsa_ttbcr_reset(CPUARMState *env, const ARMCPRegInfo *ri) { - env->cp15.c2_base_mask = 0xffffc000u; + /* Rest both the TTBCR as well as the masks corresponding to the bank of + * the TTBCR being reset. + */ + A32_BANKED_REG_SET(env, c2_base_mask, + ((ri->type & ARM_CP_BANK_S) == ARM_CP_BANK_S), + 0xffffc000u); + A32_BANKED_REG_SET(env, c2_mask, + ((ri->type & ARM_CP_BANK_S) == ARM_CP_BANK_S), 0); raw_write(env, ri, 0); - env->cp15.c2_mask = 0; } static void vmsa_tcr_el1_write(CPUARMState *env, const ARMCPRegInfo *ri, @@ -4520,7 +4532,7 @@ static bool get_level1_table_address(CPUARMState *env, uint32_t *table, * Aarch32 there is a secure and non-secure instance of the translation * table registers. */ - if (address & env->cp15.c2_mask) { + if (address & A32_BANKED_CURRENT_REG_GET(env, c2_mask)) { if (A32_BANKED_CURRENT_REG_GET(env, ttbcr) & TTBCR_PD1) { /* Translation table walk disabled for TTBR1 */ return false; @@ -4532,7 +4544,7 @@ static bool get_level1_table_address(CPUARMState *env, uint32_t *table, return false; } *table = A32_BANKED_CURRENT_REG_GET(env, ttbr0) & - env->cp15.c2_base_mask; + A32_BANKED_CURRENT_REG_GET(env, c2_base_mask); } *table |= (address >> 18) & 0x3ffc; return true; -- 1.8.3.2