From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:42977) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1XZ5JE-0000Mx-Gy for qemu-devel@nongnu.org; Tue, 30 Sep 2014 17:50:17 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1XZ5J2-0003Gw-SN for qemu-devel@nongnu.org; Tue, 30 Sep 2014 17:50:12 -0400 Received: from mail-pa0-f41.google.com ([209.85.220.41]:56732) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1XZ5J0-0003Ck-R4 for qemu-devel@nongnu.org; Tue, 30 Sep 2014 17:50:00 -0400 Received: by mail-pa0-f41.google.com with SMTP id eu11so4931335pac.0 for ; Tue, 30 Sep 2014 14:49:57 -0700 (PDT) From: Greg Bellows Date: Tue, 30 Sep 2014 16:49:14 -0500 Message-Id: <1412113785-21525-3-git-send-email-greg.bellows@linaro.org> In-Reply-To: <1412113785-21525-1-git-send-email-greg.bellows@linaro.org> References: <1412113785-21525-1-git-send-email-greg.bellows@linaro.org> Subject: [Qemu-devel] [PATCH v5 02/33] target-arm: add arm_is_secure() function List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org, peter.maydell@linaro.org, serge.fdrv@gmail.com, edgar.iglesias@gmail.com, aggelerf@ethz.ch Cc: Sergey Fedorov , Greg Bellows From: Fabian Aggeler arm_is_secure() function allows to determine CPU security state if the CPU implements Security Extensions/EL3. arm_is_secure_below_el3() returns true if CPU is in secure state below EL3. Signed-off-by: Sergey Fedorov Signed-off-by: Fabian Aggeler Signed-off-by: Greg Bellows --- target-arm/cpu.h | 38 ++++++++++++++++++++++++++++++++++++++ 1 file changed, 38 insertions(+) diff --git a/target-arm/cpu.h b/target-arm/cpu.h index 81fffd2..10afef0 100644 --- a/target-arm/cpu.h +++ b/target-arm/cpu.h @@ -753,6 +753,44 @@ static inline int arm_feature(CPUARMState *env, int feature) return (env->features & (1ULL << feature)) != 0; } + +/* Return true if exception level below EL3 is in secure state */ +static inline bool arm_is_secure_below_el3(CPUARMState *env) +{ +#if !defined(CONFIG_USER_ONLY) + if (arm_feature(env, ARM_FEATURE_EL3)) { + return !(env->cp15.scr_el3 & SCR_NS); + } else if (arm_feature(env, ARM_FEATURE_EL2)) { + return false; + } else { + /* IMPDEF: QEMU defaults to non-secure */ + return false; + } +#else + return false; +#endif +} + +/* Return true if the processor is in secure state */ +static inline bool arm_is_secure(CPUARMState *env) +{ +#if !defined(CONFIG_USER_ONLY) + if (arm_feature(env, ARM_FEATURE_EL3)) { + if (env->aarch64 && extract32(env->pstate, 2, 2) == 3) { + /* CPU currently in Aarch64 state and EL3 */ + return true; + } else if (!env->aarch64 && + (env->uncached_cpsr & CPSR_M) == ARM_CPU_MODE_MON) { + /* CPU currently in Aarch32 state and monitor mode */ + return true; + } + } + return arm_is_secure_below_el3(env); +#else + return false; +#endif +} + /* Return true if the specified exception level is running in AArch64 state. */ static inline bool arm_el_is_aa64(CPUARMState *env, int el) { -- 1.8.3.2