[Qemu-devel] [PATCH v5 32/33] target-arm: add GDB scr register

[Greg Bellows <greg.bellows@linaro.org>]

Added the ability to print the scr register like can be done with the cpsr.

Signed-off-by: Greg Bellows <greg.bellows@linaro.org>
---
 gdb-xml/arm-core.xml | 1 +
 target-arm/cpu.c     | 2 +-
 target-arm/cpu.h     | 2 ++
 target-arm/gdbstub.c | 3 +++
 target-arm/helper.c  | 5 +++++
 5 files changed, 12 insertions(+), 1 deletion(-)

diff --git a/gdb-xml/arm-core.xml b/gdb-xml/arm-core.xml
index 6012f34..b63b998 100644
--- a/gdb-xml/arm-core.xml
+++ b/gdb-xml/arm-core.xml
@@ -28,4 +28,5 @@
        the FPA registers historically were placed between the PC
        and the CPSR in the "g" packet.  -->
   <reg name="cpsr" bitsize="32" regnum="25"/>
+  <reg name="scr" bitsize="32" regnum="26"/>
 </feature>
diff --git a/target-arm/cpu.c b/target-arm/cpu.c
index 2a5c333..ea2169b 100644
--- a/target-arm/cpu.c
+++ b/target-arm/cpu.c
@@ -1116,7 +1116,7 @@ static void arm_cpu_class_init(ObjectClass *oc, void *data)
     cc->get_phys_page_debug = arm_cpu_get_phys_page_debug;
     cc->vmsd = &vmstate_arm_cpu;
 #endif
-    cc->gdb_num_core_regs = 26;
+    cc->gdb_num_core_regs = 27;
     cc->gdb_core_xml_file = "arm-core.xml";
     cc->debug_excp_handler = arm_debug_excp_handler;
 }
diff --git a/target-arm/cpu.h b/target-arm/cpu.h
index 7d27c69..8059d8a 100644
--- a/target-arm/cpu.h
+++ b/target-arm/cpu.h
@@ -689,6 +689,8 @@ static inline void pstate_write(CPUARMState *env, uint32_t val)
 
 /* Return the current CPSR value.  */
 uint32_t cpsr_read(CPUARMState *env);
+/* Return the current SCR value.  */
+uint32_t scr_read(CPUARMState *env);
 /* Set the CPSR.  Note that some bits of mask must be all-set or all-clear.  */
 void cpsr_write(CPUARMState *env, uint32_t val, uint32_t mask);
 
diff --git a/target-arm/gdbstub.c b/target-arm/gdbstub.c
index 1c34396..9fbe979 100644
--- a/target-arm/gdbstub.c
+++ b/target-arm/gdbstub.c
@@ -54,6 +54,9 @@ int arm_cpu_gdb_read_register(CPUState *cs, uint8_t *mem_buf, int n)
     case 25:
         /* CPSR */
         return gdb_get_reg32(mem_buf, cpsr_read(env));
+    case 26:
+        /* SCR */
+        return gdb_get_reg32(mem_buf, scr_read(env));
     }
     /* Unknown register.  */
     return 0;
diff --git a/target-arm/helper.c b/target-arm/helper.c
index 8d9563f..a721db1 100644
--- a/target-arm/helper.c
+++ b/target-arm/helper.c
@@ -2407,6 +2407,11 @@ static const ARMCPRegInfo v8_el2_cp_reginfo[] = {
     REGINFO_SENTINEL
 };
 
+uint32_t scr_read(CPUARMState *env)
+{
+    return env->cp15.scr_el3;
+}
+
 static void nsacr_write(CPUARMState *env, const ARMCPRegInfo *ri,
                       uint64_t value)
 {
-- 
1.8.3.2