From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:43662) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1XZ5K4-0001N8-AX for qemu-devel@nongnu.org; Tue, 30 Sep 2014 17:51:10 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1XZ5Jy-000472-7S for qemu-devel@nongnu.org; Tue, 30 Sep 2014 17:51:04 -0400 Received: from mail-pa0-f54.google.com ([209.85.220.54]:57310) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1XZ5Jx-000456-Ps for qemu-devel@nongnu.org; Tue, 30 Sep 2014 17:50:58 -0400 Received: by mail-pa0-f54.google.com with SMTP id ey11so8752935pad.27 for ; Tue, 30 Sep 2014 14:50:43 -0700 (PDT) From: Greg Bellows Date: Tue, 30 Sep 2014 16:49:44 -0500 Message-Id: <1412113785-21525-33-git-send-email-greg.bellows@linaro.org> In-Reply-To: <1412113785-21525-1-git-send-email-greg.bellows@linaro.org> References: <1412113785-21525-1-git-send-email-greg.bellows@linaro.org> Subject: [Qemu-devel] [PATCH v5 32/33] target-arm: add GDB scr register List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org, peter.maydell@linaro.org, serge.fdrv@gmail.com, edgar.iglesias@gmail.com, aggelerf@ethz.ch Cc: Greg Bellows Added the ability to print the scr register like can be done with the cpsr. Signed-off-by: Greg Bellows --- gdb-xml/arm-core.xml | 1 + target-arm/cpu.c | 2 +- target-arm/cpu.h | 2 ++ target-arm/gdbstub.c | 3 +++ target-arm/helper.c | 5 +++++ 5 files changed, 12 insertions(+), 1 deletion(-) diff --git a/gdb-xml/arm-core.xml b/gdb-xml/arm-core.xml index 6012f34..b63b998 100644 --- a/gdb-xml/arm-core.xml +++ b/gdb-xml/arm-core.xml @@ -28,4 +28,5 @@ the FPA registers historically were placed between the PC and the CPSR in the "g" packet. --> + diff --git a/target-arm/cpu.c b/target-arm/cpu.c index 2a5c333..ea2169b 100644 --- a/target-arm/cpu.c +++ b/target-arm/cpu.c @@ -1116,7 +1116,7 @@ static void arm_cpu_class_init(ObjectClass *oc, void *data) cc->get_phys_page_debug = arm_cpu_get_phys_page_debug; cc->vmsd = &vmstate_arm_cpu; #endif - cc->gdb_num_core_regs = 26; + cc->gdb_num_core_regs = 27; cc->gdb_core_xml_file = "arm-core.xml"; cc->debug_excp_handler = arm_debug_excp_handler; } diff --git a/target-arm/cpu.h b/target-arm/cpu.h index 7d27c69..8059d8a 100644 --- a/target-arm/cpu.h +++ b/target-arm/cpu.h @@ -689,6 +689,8 @@ static inline void pstate_write(CPUARMState *env, uint32_t val) /* Return the current CPSR value. */ uint32_t cpsr_read(CPUARMState *env); +/* Return the current SCR value. */ +uint32_t scr_read(CPUARMState *env); /* Set the CPSR. Note that some bits of mask must be all-set or all-clear. */ void cpsr_write(CPUARMState *env, uint32_t val, uint32_t mask); diff --git a/target-arm/gdbstub.c b/target-arm/gdbstub.c index 1c34396..9fbe979 100644 --- a/target-arm/gdbstub.c +++ b/target-arm/gdbstub.c @@ -54,6 +54,9 @@ int arm_cpu_gdb_read_register(CPUState *cs, uint8_t *mem_buf, int n) case 25: /* CPSR */ return gdb_get_reg32(mem_buf, cpsr_read(env)); + case 26: + /* SCR */ + return gdb_get_reg32(mem_buf, scr_read(env)); } /* Unknown register. */ return 0; diff --git a/target-arm/helper.c b/target-arm/helper.c index 8d9563f..a721db1 100644 --- a/target-arm/helper.c +++ b/target-arm/helper.c @@ -2407,6 +2407,11 @@ static const ARMCPRegInfo v8_el2_cp_reginfo[] = { REGINFO_SENTINEL }; +uint32_t scr_read(CPUARMState *env) +{ + return env->cp15.scr_el3; +} + static void nsacr_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value) { -- 1.8.3.2