From: Leon Alrae <leon.alrae@imgtec.com>
To: qemu-devel@nongnu.org
Cc: james.hogan@imgtec.com, yongbok.kim@imgtec.com,
cristian.cuna@imgtec.com, leon.alrae@imgtec.com,
aurelien@aurel32.net, rth@twiddle.net
Subject: [Qemu-devel] [PATCH v4 02/21] target-mips: signal RI Exception on instructions removed in R6
Date: Wed, 8 Oct 2014 11:55:13 +0100 [thread overview]
Message-ID: <1412765732-45369-3-git-send-email-leon.alrae@imgtec.com> (raw)
In-Reply-To: <1412765732-45369-1-git-send-email-leon.alrae@imgtec.com>
Signal Reserved Instruction Exception on instructions that do not exist in R6.
In this commit the following groups of preR6 instructions are marked as deleted:
- Floating Point Paired Single
- Floating Point Compare
- conditional moves / branches on FPU conditions
- branch likelies
- unaligned loads / stores
- traps
- legacy accumulator instructions
- COP1X
- MIPS-3D
Signed-off-by: Leon Alrae <leon.alrae@imgtec.com>
Reviewed-by: Aurelien Jarno <aurelien@aurel32.net>
---
target-mips/translate.c | 64 ++++++++++++++++++++++++++++++++++++++++++-------
1 file changed, 56 insertions(+), 8 deletions(-)
diff --git a/target-mips/translate.c b/target-mips/translate.c
index 06db150..de11747 100644
--- a/target-mips/translate.c
+++ b/target-mips/translate.c
@@ -1436,6 +1436,16 @@ static inline void check_insn(DisasContext *ctx, int flags)
}
}
+/* This code generates a "reserved instruction" exception if the
+ CPU has corresponding flag set which indicates that the instruction
+ has been removed. */
+static inline void check_insn_opc_removed(DisasContext *ctx, int flags)
+{
+ if (unlikely(ctx->insn_flags & flags)) {
+ generate_exception(ctx, EXCP_RI);
+ }
+}
+
/* This code generates a "reserved instruction" exception if 64-bit
instructions are not enabled. */
static inline void check_mips_64(DisasContext *ctx)
@@ -7712,10 +7722,12 @@ static void gen_farith (DisasContext *ctx, enum fopcode op1,
opn = "floor.w.s";
break;
case OPC_MOVCF_S:
+ check_insn_opc_removed(ctx, ISA_MIPS32R6);
gen_movcf_s(fs, fd, (ft >> 2) & 0x7, ft & 0x1);
opn = "movcf.s";
break;
case OPC_MOVZ_S:
+ check_insn_opc_removed(ctx, ISA_MIPS32R6);
{
int l1 = gen_new_label();
TCGv_i32 fp0;
@@ -7732,6 +7744,7 @@ static void gen_farith (DisasContext *ctx, enum fopcode op1,
opn = "movz.s";
break;
case OPC_MOVN_S:
+ check_insn_opc_removed(ctx, ISA_MIPS32R6);
{
int l1 = gen_new_label();
TCGv_i32 fp0;
@@ -7865,6 +7878,7 @@ static void gen_farith (DisasContext *ctx, enum fopcode op1,
opn = "cvt.l.s";
break;
case OPC_CVT_PS_S:
+ check_insn_opc_removed(ctx, ISA_MIPS32R6);
check_cp1_64bitmode(ctx);
{
TCGv_i64 fp64 = tcg_temp_new_i64();
@@ -7897,6 +7911,7 @@ static void gen_farith (DisasContext *ctx, enum fopcode op1,
case OPC_CMP_NGE_S:
case OPC_CMP_LE_S:
case OPC_CMP_NGT_S:
+ check_insn_opc_removed(ctx, ISA_MIPS32R6);
if (ctx->opcode & (1 << 6)) {
gen_cmpabs_s(ctx, func-48, ft, fs, cc);
opn = condnames_abs[func-48];
@@ -8121,10 +8136,12 @@ static void gen_farith (DisasContext *ctx, enum fopcode op1,
opn = "floor.w.d";
break;
case OPC_MOVCF_D:
+ check_insn_opc_removed(ctx, ISA_MIPS32R6);
gen_movcf_d(ctx, fs, fd, (ft >> 2) & 0x7, ft & 0x1);
opn = "movcf.d";
break;
case OPC_MOVZ_D:
+ check_insn_opc_removed(ctx, ISA_MIPS32R6);
{
int l1 = gen_new_label();
TCGv_i64 fp0;
@@ -8141,6 +8158,7 @@ static void gen_farith (DisasContext *ctx, enum fopcode op1,
opn = "movz.d";
break;
case OPC_MOVN_D:
+ check_insn_opc_removed(ctx, ISA_MIPS32R6);
{
int l1 = gen_new_label();
TCGv_i64 fp0;
@@ -8250,6 +8268,7 @@ static void gen_farith (DisasContext *ctx, enum fopcode op1,
case OPC_CMP_NGE_D:
case OPC_CMP_LE_D:
case OPC_CMP_NGT_D:
+ check_insn_opc_removed(ctx, ISA_MIPS32R6);
if (ctx->opcode & (1 << 6)) {
gen_cmpabs_d(ctx, func-48, ft, fs, cc);
opn = condnames_abs[func-48];
@@ -8350,6 +8369,7 @@ static void gen_farith (DisasContext *ctx, enum fopcode op1,
opn = "cvt.d.l";
break;
case OPC_CVT_PS_PW:
+ check_insn_opc_removed(ctx, ISA_MIPS32R6);
check_cp1_64bitmode(ctx);
{
TCGv_i64 fp0 = tcg_temp_new_i64();
@@ -14508,6 +14528,7 @@ static void decode_opc (CPUMIPSState *env, DisasContext *ctx)
break;
case OPC_MOVN: /* Conditional move */
case OPC_MOVZ:
+ check_insn_opc_removed(ctx, ISA_MIPS32R6);
check_insn(ctx, ISA_MIPS4 | ISA_MIPS32 |
INSN_LOONGSON2E | INSN_LOONGSON2F);
gen_cond_move(ctx, op1, rd, rs, rt);
@@ -14568,10 +14589,12 @@ static void decode_opc (CPUMIPSState *env, DisasContext *ctx)
break;
case OPC_MFHI: /* Move from HI/LO */
case OPC_MFLO:
+ check_insn_opc_removed(ctx, ISA_MIPS32R6);
gen_HILO(ctx, op1, rs & 3, rd);
break;
case OPC_MTHI:
case OPC_MTLO: /* Move to HI/LO */
+ check_insn_opc_removed(ctx, ISA_MIPS32R6);
gen_HILO(ctx, op1, rd & 3, rs);
break;
case OPC_PMON: /* Pmon entry point, also R4010 selsl */
@@ -14604,6 +14627,7 @@ static void decode_opc (CPUMIPSState *env, DisasContext *ctx)
break;
case OPC_MOVCI:
+ check_insn_opc_removed(ctx, ISA_MIPS32R6);
check_insn(ctx, ISA_MIPS4 | ISA_MIPS32);
if (ctx->CP0_Config1 & (1 << CP0C1_FP)) {
check_cp1_enabled(ctx);
@@ -14706,10 +14730,12 @@ static void decode_opc (CPUMIPSState *env, DisasContext *ctx)
switch (op1) {
case OPC_MADD ... OPC_MADDU: /* Multiply and add/sub */
case OPC_MSUB ... OPC_MSUBU:
+ check_insn_opc_removed(ctx, ISA_MIPS32R6);
check_insn(ctx, ISA_MIPS32);
gen_muldiv(ctx, op1, rd & 3, rs, rt);
break;
case OPC_MUL:
+ check_insn_opc_removed(ctx, ISA_MIPS32R6);
gen_arith(ctx, op1, rd, rs, rt);
break;
case OPC_CLO:
@@ -15327,12 +15353,20 @@ static void decode_opc (CPUMIPSState *env, DisasContext *ctx)
case OPC_REGIMM:
op1 = MASK_REGIMM(ctx->opcode);
switch (op1) {
- case OPC_BLTZ ... OPC_BGEZL: /* REGIMM branches */
- case OPC_BLTZAL ... OPC_BGEZALL:
+ case OPC_BLTZL: /* REGIMM branches */
+ case OPC_BGEZL:
+ case OPC_BLTZALL:
+ case OPC_BGEZALL:
+ check_insn_opc_removed(ctx, ISA_MIPS32R6);
+ case OPC_BLTZ:
+ case OPC_BGEZ:
+ case OPC_BLTZAL:
+ case OPC_BGEZAL:
gen_compute_branch(ctx, op1, 4, rs, -1, imm << 2);
break;
case OPC_TGEI ... OPC_TEQI: /* REGIMM traps */
case OPC_TNEI:
+ check_insn_opc_removed(ctx, ISA_MIPS32R6);
gen_trap(ctx, op1, rs, -1, imm);
break;
case OPC_SYNCI:
@@ -15457,16 +15491,24 @@ static void decode_opc (CPUMIPSState *env, DisasContext *ctx)
offset = (int32_t)(ctx->opcode & 0x3FFFFFF) << 2;
gen_compute_branch(ctx, op, 4, rs, rt, offset);
break;
- case OPC_BEQ ... OPC_BGTZ: /* Branch */
- case OPC_BEQL ... OPC_BGTZL:
+ case OPC_BEQL ... OPC_BGTZL: /* Branch */
+ check_insn_opc_removed(ctx, ISA_MIPS32R6);
+ case OPC_BEQ ... OPC_BGTZ:
gen_compute_branch(ctx, op, 4, rs, rt, imm << 2);
break;
- case OPC_LB ... OPC_LWR: /* Load and stores */
+ case OPC_LWL: /* Load and stores */
+ case OPC_LWR:
+ check_insn_opc_removed(ctx, ISA_MIPS32R6);
+ case OPC_LB ... OPC_LH:
+ case OPC_LW ... OPC_LHU:
case OPC_LL:
gen_ld(ctx, op, rt, rs, imm);
break;
- case OPC_SB ... OPC_SW:
+ case OPC_SWL:
case OPC_SWR:
+ check_insn_opc_removed(ctx, ISA_MIPS32R6);
+ case OPC_SB ... OPC_SH:
+ case OPC_SW:
gen_st(ctx, op, rt, rs, imm);
break;
case OPC_SC:
@@ -15513,18 +15555,21 @@ static void decode_opc (CPUMIPSState *env, DisasContext *ctx)
#endif
case OPC_BC1ANY2:
case OPC_BC1ANY4:
+ check_insn_opc_removed(ctx, ISA_MIPS32R6);
check_cop1x(ctx);
check_insn(ctx, ASE_MIPS3D);
/* fall through */
case OPC_BC1:
+ check_insn_opc_removed(ctx, ISA_MIPS32R6);
gen_compute_branch1(ctx, MASK_BC1(ctx->opcode),
(rt >> 2) & 0x7, imm << 2);
break;
+ case OPC_PS_FMT:
+ check_insn_opc_removed(ctx, ISA_MIPS32R6);
case OPC_S_FMT:
case OPC_D_FMT:
case OPC_W_FMT:
case OPC_L_FMT:
- case OPC_PS_FMT:
gen_farith(ctx, ctx->opcode & FOP(0x3f, 0x1f), rt, rd, sa,
(imm >> 8) & 0x7);
break;
@@ -15553,6 +15598,7 @@ static void decode_opc (CPUMIPSState *env, DisasContext *ctx)
break;
case OPC_CP3:
+ check_insn_opc_removed(ctx, ISA_MIPS32R6);
if (ctx->CP0_Config1 & (1 << CP0C1_FP)) {
check_cp1_enabled(ctx);
op1 = MASK_CP3(ctx->opcode);
@@ -15595,8 +15641,9 @@ static void decode_opc (CPUMIPSState *env, DisasContext *ctx)
#if defined(TARGET_MIPS64)
/* MIPS64 opcodes */
- case OPC_LWU:
case OPC_LDL ... OPC_LDR:
+ check_insn_opc_removed(ctx, ISA_MIPS32R6);
+ case OPC_LWU:
case OPC_LLD:
case OPC_LD:
check_insn(ctx, ISA_MIPS3);
@@ -15604,6 +15651,7 @@ static void decode_opc (CPUMIPSState *env, DisasContext *ctx)
gen_ld(ctx, op, rt, rs, imm);
break;
case OPC_SDL ... OPC_SDR:
+ check_insn_opc_removed(ctx, ISA_MIPS32R6);
case OPC_SD:
check_insn(ctx, ISA_MIPS3);
check_mips_64(ctx);
--
2.1.0
next prev parent reply other threads:[~2014-10-08 10:56 UTC|newest]
Thread overview: 27+ messages / expand[flat|nested] mbox.gz Atom feed top
2014-10-08 10:55 [Qemu-devel] [PATCH v4 00/21] target-mips: add MIPS64R6 Instruction Set support Leon Alrae
2014-10-08 10:55 ` [Qemu-devel] [PATCH v4 01/21] target-mips: define ISA_MIPS64R6 Leon Alrae
2014-10-08 10:55 ` Leon Alrae [this message]
2014-10-08 10:55 ` [Qemu-devel] [PATCH v4 03/21] target-mips: add SELEQZ and SELNEZ instructions Leon Alrae
2014-10-08 10:55 ` [Qemu-devel] [PATCH v4 04/21] target-mips: move LL and SC instructions Leon Alrae
2014-10-08 10:55 ` [Qemu-devel] [PATCH v4 05/21] target-mips: extract decode_opc_special* from decode_opc Leon Alrae
2014-10-08 10:55 ` [Qemu-devel] [PATCH v4 06/21] target-mips: split decode_opc_special* into *_r6 and *_legacy Leon Alrae
2014-10-08 10:55 ` [Qemu-devel] [PATCH v4 07/21] target-mips: signal RI Exception on DSP and Loongson instructions Leon Alrae
2014-10-08 10:55 ` [Qemu-devel] [PATCH v4 08/21] target-mips: move PREF, CACHE, LLD and SCD instructions Leon Alrae
2014-10-08 10:55 ` [Qemu-devel] [PATCH v4 09/21] target-mips: redefine Integer Multiply and Divide instructions Leon Alrae
2014-10-08 10:55 ` [Qemu-devel] [PATCH v4 10/21] target-mips: move CLO, DCLO, CLZ, DCLZ, SDBBP and free special2 in R6 Leon Alrae
2014-10-08 10:55 ` [Qemu-devel] [PATCH v4 11/21] target-mips: Status.UX/SX/KX enable 32-bit address wrapping Leon Alrae
2014-10-08 10:55 ` [Qemu-devel] [PATCH v4 12/21] target-mips: add ALIGN, DALIGN, BITSWAP and DBITSWAP instructions Leon Alrae
2014-10-08 10:55 ` [Qemu-devel] [PATCH v4 13/21] target-mips: add compact and CP1 branches Leon Alrae
2014-10-08 10:55 ` [Qemu-devel] [PATCH v4 14/21] target-mips: add AUI, LSA and PCREL instruction families Leon Alrae
2014-10-13 13:37 ` Yongbok Kim
2014-10-14 11:40 ` Leon Alrae
2014-11-12 21:07 ` Paolo Bonzini
2014-11-13 10:39 ` Leon Alrae
2014-10-08 10:55 ` [Qemu-devel] [PATCH v4 15/21] softfloat: add functions corresponding to IEEE-2008 min/maxNumMag Leon Alrae
2014-10-08 10:55 ` [Qemu-devel] [PATCH v4 16/21] target-mips: add new Floating Point instructions Leon Alrae
2014-10-08 10:55 ` [Qemu-devel] [PATCH v4 17/21] target-mips: add new Floating Point Comparison instructions Leon Alrae
2014-10-08 10:55 ` [Qemu-devel] [PATCH v4 18/21] target-mips: do not allow Status.FR=0 mode in 64-bit FPU Leon Alrae
2014-10-08 10:55 ` [Qemu-devel] [PATCH v4 19/21] target-mips: remove JR, BLTZAL, BGEZAL and add NAL, BAL instructions Leon Alrae
2014-10-08 10:55 ` [Qemu-devel] [PATCH v4 20/21] mips_malta: update malta's pseudo-bootloader - replace JR with JALR Leon Alrae
2014-10-08 10:55 ` [Qemu-devel] [PATCH v4 21/21] target-mips: define a new generic CPU supporting MIPS64 Release 6 ISA Leon Alrae
2014-10-14 9:05 ` Yongbok Kim
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