From: Leon Alrae <leon.alrae@imgtec.com>
To: qemu-devel@nongnu.org
Cc: james.hogan@imgtec.com, yongbok.kim@imgtec.com,
cristian.cuna@imgtec.com, leon.alrae@imgtec.com,
aurelien@aurel32.net, rth@twiddle.net
Subject: [Qemu-devel] [PATCH v4 07/21] target-mips: signal RI Exception on DSP and Loongson instructions
Date: Wed, 8 Oct 2014 11:55:18 +0100 [thread overview]
Message-ID: <1412765732-45369-8-git-send-email-leon.alrae@imgtec.com> (raw)
In-Reply-To: <1412765732-45369-1-git-send-email-leon.alrae@imgtec.com>
Move DSP and Loongson instruction to *_legacy functions as they have been
removed in R6.
Signed-off-by: Leon Alrae <leon.alrae@imgtec.com>
Reviewed-by: Aurelien Jarno <aurelien@aurel32.net>
---
target-mips/translate.c | 195 ++++++++++++++++++++++++------------------------
1 file changed, 98 insertions(+), 97 deletions(-)
diff --git a/target-mips/translate.c b/target-mips/translate.c
index 0c64aeb..11967a0 100644
--- a/target-mips/translate.c
+++ b/target-mips/translate.c
@@ -14783,6 +14783,26 @@ static void decode_opc_special2_legacy(CPUMIPSState *env, DisasContext *ctx)
case OPC_MUL:
gen_arith(ctx, op1, rd, rs, rt);
break;
+ case OPC_DIV_G_2F:
+ case OPC_DIVU_G_2F:
+ case OPC_MULT_G_2F:
+ case OPC_MULTU_G_2F:
+ case OPC_MOD_G_2F:
+ case OPC_MODU_G_2F:
+ check_insn(ctx, INSN_LOONGSON2F);
+ gen_loongson_integer(ctx, op1, rd, rs, rt);
+ break;
+#if defined(TARGET_MIPS64)
+ case OPC_DMULT_G_2F:
+ case OPC_DMULTU_G_2F:
+ case OPC_DDIV_G_2F:
+ case OPC_DDIVU_G_2F:
+ case OPC_DMOD_G_2F:
+ case OPC_DMODU_G_2F:
+ check_insn(ctx, INSN_LOONGSON2F);
+ gen_loongson_integer(ctx, op1, rd, rs, rt);
+ break;
+#endif
default: /* Invalid */
MIPS_INVAL("special2_legacy");
generate_exception(ctx, EXCP_RI);
@@ -14792,11 +14812,10 @@ static void decode_opc_special2_legacy(CPUMIPSState *env, DisasContext *ctx)
static void decode_opc_special2(CPUMIPSState *env, DisasContext *ctx)
{
- int rs, rt, rd;
+ int rs, rd;
uint32_t op1;
rs = (ctx->opcode >> 21) & 0x1f;
- rt = (ctx->opcode >> 16) & 0x1f;
rd = (ctx->opcode >> 11) & 0x1f;
op1 = MASK_SPECIAL2(ctx->opcode);
@@ -14818,15 +14837,6 @@ static void decode_opc_special2(CPUMIPSState *env, DisasContext *ctx)
}
/* Treat as NOP. */
break;
- case OPC_DIV_G_2F:
- case OPC_DIVU_G_2F:
- case OPC_MULT_G_2F:
- case OPC_MULTU_G_2F:
- case OPC_MOD_G_2F:
- case OPC_MODU_G_2F:
- check_insn(ctx, INSN_LOONGSON2F);
- gen_loongson_integer(ctx, op1, rd, rs, rt);
- break;
#if defined(TARGET_MIPS64)
case OPC_DCLO:
case OPC_DCLZ:
@@ -14834,15 +14844,6 @@ static void decode_opc_special2(CPUMIPSState *env, DisasContext *ctx)
check_mips_64(ctx);
gen_cl(ctx, op1, rd, rs);
break;
- case OPC_DMULT_G_2F:
- case OPC_DMULTU_G_2F:
- case OPC_DDIV_G_2F:
- case OPC_DDIVU_G_2F:
- case OPC_DMOD_G_2F:
- case OPC_DMODU_G_2F:
- check_insn(ctx, INSN_LOONGSON2F);
- gen_loongson_integer(ctx, op1, rd, rs, rt);
- break;
#endif
default:
if (ctx->insn_flags & ISA_MIPS32R6) {
@@ -14880,80 +14881,15 @@ static void decode_opc_special3_r6(CPUMIPSState *env, DisasContext *ctx)
static void decode_opc_special3_legacy(CPUMIPSState *env, DisasContext *ctx)
{
- uint32_t op1;
-#if defined(TARGET_MIPS64)
- int rd = (ctx->opcode >> 11) & 0x1f;
- int rs = (ctx->opcode >> 21) & 0x1f;
- int rt = (ctx->opcode >> 16) & 0x1f;
-#endif
-
- op1 = MASK_SPECIAL3(ctx->opcode);
- switch (op1) {
-#if defined(TARGET_MIPS64)
- case OPC_DDIV_G_2E ... OPC_DDIVU_G_2E:
- case OPC_DMULT_G_2E ... OPC_DMULTU_G_2E:
- case OPC_DMOD_G_2E ... OPC_DMODU_G_2E:
- check_insn(ctx, INSN_LOONGSON2E);
- gen_loongson_integer(ctx, op1, rd, rs, rt);
- break;
-#endif
- default: /* Invalid */
- MIPS_INVAL("special3_legacy");
- generate_exception(ctx, EXCP_RI);
- break;
- }
-}
-
-static void decode_opc_special3(CPUMIPSState *env, DisasContext *ctx)
-{
- int rs, rt, rd, sa;
+ int rs, rt, rd;
uint32_t op1, op2;
rs = (ctx->opcode >> 21) & 0x1f;
rt = (ctx->opcode >> 16) & 0x1f;
rd = (ctx->opcode >> 11) & 0x1f;
- sa = (ctx->opcode >> 6) & 0x1f;
op1 = MASK_SPECIAL3(ctx->opcode);
switch (op1) {
- case OPC_EXT:
- case OPC_INS:
- check_insn(ctx, ISA_MIPS32R2);
- gen_bitops(ctx, op1, rt, rs, sa, rd);
- break;
- case OPC_BSHFL:
- check_insn(ctx, ISA_MIPS32R2);
- op2 = MASK_BSHFL(ctx->opcode);
- gen_bshfl(ctx, op2, rt, rd);
- break;
- case OPC_RDHWR:
- gen_rdhwr(ctx, rt, rd);
- break;
- case OPC_FORK:
- check_insn(ctx, ASE_MT);
- {
- TCGv t0 = tcg_temp_new();
- TCGv t1 = tcg_temp_new();
-
- gen_load_gpr(t0, rt);
- gen_load_gpr(t1, rs);
- gen_helper_fork(t0, t1);
- tcg_temp_free(t0);
- tcg_temp_free(t1);
- }
- break;
- case OPC_YIELD:
- check_insn(ctx, ASE_MT);
- {
- TCGv t0 = tcg_temp_new();
-
- save_cpu_state(ctx, 1);
- gen_load_gpr(t0, rs);
- gen_helper_yield(t0, cpu_env, t0);
- gen_store_gpr(t0, rd);
- tcg_temp_free(t0);
- }
- break;
case OPC_DIV_G_2E ... OPC_DIVU_G_2E:
case OPC_MOD_G_2E ... OPC_MODU_G_2E:
case OPC_MULT_G_2E ... OPC_MULTU_G_2E:
@@ -15221,17 +15157,11 @@ static void decode_opc_special3(CPUMIPSState *env, DisasContext *ctx)
}
break;
#if defined(TARGET_MIPS64)
- case OPC_DEXTM ... OPC_DEXT:
- case OPC_DINSM ... OPC_DINS:
- check_insn(ctx, ISA_MIPS64R2);
- check_mips_64(ctx);
- gen_bitops(ctx, op1, rt, rs, sa, rd);
- break;
- case OPC_DBSHFL:
- check_insn(ctx, ISA_MIPS64R2);
- check_mips_64(ctx);
- op2 = MASK_DBSHFL(ctx->opcode);
- gen_bshfl(ctx, op2, rt, rd);
+ case OPC_DDIV_G_2E ... OPC_DDIVU_G_2E:
+ case OPC_DMULT_G_2E ... OPC_DMULTU_G_2E:
+ case OPC_DMOD_G_2E ... OPC_DMODU_G_2E:
+ check_insn(ctx, INSN_LOONGSON2E);
+ gen_loongson_integer(ctx, op1, rd, rs, rt);
break;
case OPC_ABSQ_S_QH_DSP:
op2 = MASK_ABSQ_S_QH(ctx->opcode);
@@ -15464,6 +15394,77 @@ static void decode_opc_special3(CPUMIPSState *env, DisasContext *ctx)
gen_mipsdsp_shift(ctx, op1, rd, rs, rt);
break;
#endif
+ default: /* Invalid */
+ MIPS_INVAL("special3_legacy");
+ generate_exception(ctx, EXCP_RI);
+ break;
+ }
+}
+
+static void decode_opc_special3(CPUMIPSState *env, DisasContext *ctx)
+{
+ int rs, rt, rd, sa;
+ uint32_t op1, op2;
+
+ rs = (ctx->opcode >> 21) & 0x1f;
+ rt = (ctx->opcode >> 16) & 0x1f;
+ rd = (ctx->opcode >> 11) & 0x1f;
+ sa = (ctx->opcode >> 6) & 0x1f;
+
+ op1 = MASK_SPECIAL3(ctx->opcode);
+ switch (op1) {
+ case OPC_EXT:
+ case OPC_INS:
+ check_insn(ctx, ISA_MIPS32R2);
+ gen_bitops(ctx, op1, rt, rs, sa, rd);
+ break;
+ case OPC_BSHFL:
+ check_insn(ctx, ISA_MIPS32R2);
+ op2 = MASK_BSHFL(ctx->opcode);
+ gen_bshfl(ctx, op2, rt, rd);
+ break;
+#if defined(TARGET_MIPS64)
+ case OPC_DEXTM ... OPC_DEXT:
+ case OPC_DINSM ... OPC_DINS:
+ check_insn(ctx, ISA_MIPS64R2);
+ check_mips_64(ctx);
+ gen_bitops(ctx, op1, rt, rs, sa, rd);
+ break;
+ case OPC_DBSHFL:
+ check_insn(ctx, ISA_MIPS64R2);
+ check_mips_64(ctx);
+ op2 = MASK_DBSHFL(ctx->opcode);
+ gen_bshfl(ctx, op2, rt, rd);
+ break;
+#endif
+ case OPC_RDHWR:
+ gen_rdhwr(ctx, rt, rd);
+ break;
+ case OPC_FORK:
+ check_insn(ctx, ASE_MT);
+ {
+ TCGv t0 = tcg_temp_new();
+ TCGv t1 = tcg_temp_new();
+
+ gen_load_gpr(t0, rt);
+ gen_load_gpr(t1, rs);
+ gen_helper_fork(t0, t1);
+ tcg_temp_free(t0);
+ tcg_temp_free(t1);
+ }
+ break;
+ case OPC_YIELD:
+ check_insn(ctx, ASE_MT);
+ {
+ TCGv t0 = tcg_temp_new();
+
+ save_cpu_state(ctx, 1);
+ gen_load_gpr(t0, rs);
+ gen_helper_yield(t0, cpu_env, t0);
+ gen_store_gpr(t0, rd);
+ tcg_temp_free(t0);
+ }
+ break;
default:
if (ctx->insn_flags & ISA_MIPS32R6) {
decode_opc_special3_r6(env, ctx);
--
2.1.0
next prev parent reply other threads:[~2014-10-08 10:56 UTC|newest]
Thread overview: 27+ messages / expand[flat|nested] mbox.gz Atom feed top
2014-10-08 10:55 [Qemu-devel] [PATCH v4 00/21] target-mips: add MIPS64R6 Instruction Set support Leon Alrae
2014-10-08 10:55 ` [Qemu-devel] [PATCH v4 01/21] target-mips: define ISA_MIPS64R6 Leon Alrae
2014-10-08 10:55 ` [Qemu-devel] [PATCH v4 02/21] target-mips: signal RI Exception on instructions removed in R6 Leon Alrae
2014-10-08 10:55 ` [Qemu-devel] [PATCH v4 03/21] target-mips: add SELEQZ and SELNEZ instructions Leon Alrae
2014-10-08 10:55 ` [Qemu-devel] [PATCH v4 04/21] target-mips: move LL and SC instructions Leon Alrae
2014-10-08 10:55 ` [Qemu-devel] [PATCH v4 05/21] target-mips: extract decode_opc_special* from decode_opc Leon Alrae
2014-10-08 10:55 ` [Qemu-devel] [PATCH v4 06/21] target-mips: split decode_opc_special* into *_r6 and *_legacy Leon Alrae
2014-10-08 10:55 ` Leon Alrae [this message]
2014-10-08 10:55 ` [Qemu-devel] [PATCH v4 08/21] target-mips: move PREF, CACHE, LLD and SCD instructions Leon Alrae
2014-10-08 10:55 ` [Qemu-devel] [PATCH v4 09/21] target-mips: redefine Integer Multiply and Divide instructions Leon Alrae
2014-10-08 10:55 ` [Qemu-devel] [PATCH v4 10/21] target-mips: move CLO, DCLO, CLZ, DCLZ, SDBBP and free special2 in R6 Leon Alrae
2014-10-08 10:55 ` [Qemu-devel] [PATCH v4 11/21] target-mips: Status.UX/SX/KX enable 32-bit address wrapping Leon Alrae
2014-10-08 10:55 ` [Qemu-devel] [PATCH v4 12/21] target-mips: add ALIGN, DALIGN, BITSWAP and DBITSWAP instructions Leon Alrae
2014-10-08 10:55 ` [Qemu-devel] [PATCH v4 13/21] target-mips: add compact and CP1 branches Leon Alrae
2014-10-08 10:55 ` [Qemu-devel] [PATCH v4 14/21] target-mips: add AUI, LSA and PCREL instruction families Leon Alrae
2014-10-13 13:37 ` Yongbok Kim
2014-10-14 11:40 ` Leon Alrae
2014-11-12 21:07 ` Paolo Bonzini
2014-11-13 10:39 ` Leon Alrae
2014-10-08 10:55 ` [Qemu-devel] [PATCH v4 15/21] softfloat: add functions corresponding to IEEE-2008 min/maxNumMag Leon Alrae
2014-10-08 10:55 ` [Qemu-devel] [PATCH v4 16/21] target-mips: add new Floating Point instructions Leon Alrae
2014-10-08 10:55 ` [Qemu-devel] [PATCH v4 17/21] target-mips: add new Floating Point Comparison instructions Leon Alrae
2014-10-08 10:55 ` [Qemu-devel] [PATCH v4 18/21] target-mips: do not allow Status.FR=0 mode in 64-bit FPU Leon Alrae
2014-10-08 10:55 ` [Qemu-devel] [PATCH v4 19/21] target-mips: remove JR, BLTZAL, BGEZAL and add NAL, BAL instructions Leon Alrae
2014-10-08 10:55 ` [Qemu-devel] [PATCH v4 20/21] mips_malta: update malta's pseudo-bootloader - replace JR with JALR Leon Alrae
2014-10-08 10:55 ` [Qemu-devel] [PATCH v4 21/21] target-mips: define a new generic CPU supporting MIPS64 Release 6 ISA Leon Alrae
2014-10-14 9:05 ` Yongbok Kim
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