From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:34848) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Xccfi-0006mT-R1 for qemu-devel@nongnu.org; Fri, 10 Oct 2014 12:04:13 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1Xccfc-0007vs-5K for qemu-devel@nongnu.org; Fri, 10 Oct 2014 12:04:02 -0400 Received: from mail-oi0-f53.google.com ([209.85.218.53]:45471) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Xccfc-0007vc-1T for qemu-devel@nongnu.org; Fri, 10 Oct 2014 12:03:56 -0400 Received: by mail-oi0-f53.google.com with SMTP id v63so6866672oia.26 for ; Fri, 10 Oct 2014 09:03:54 -0700 (PDT) From: Greg Bellows Date: Fri, 10 Oct 2014 11:03:11 -0500 Message-Id: <1412957023-11105-1-git-send-email-greg.bellows@linaro.org> Subject: [Qemu-devel] [PATCH v6 00/32] target-arm: add Security Extensions for CPUs List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org, peter.maydell@linaro.org, serge.fdrv@gmail.com, edgar.iglesias@gmail.com, aggelerf@ethz.ch Version 6 of the ARM processor security extension (TrustZone) support. This patchset includes changes to support the processor security extensions on ARMv7 aarch32 with hooks for later enabling v8 aarch64/32. Summary of generic changes from v5 -> v6: - Removed patch v5 32/33 (add GDB scr register) - Separated CPREG secure support handling to its own commit - Addressed review feedback - Added/fixed comments and commit messages More detailed change history included on a per-patch basis. Fabian Aggeler (26): target-arm: increase arrays of registers R13 & R14 target-arm: add arm_is_secure() function target-arm: make arm_current_el() return EL3 target-arm: A32: Emulate the SMC instruction target-arm: extend async excp masking target-arm: add async excp target_el function target-arm: add banked register accessors target-arm: add CPREG secure state support target-arm: insert AArch32 cpregs twice into hashtable target-arm: move AArch32 SCR into security reglist target-arm: implement IRQ/FIQ routing to Monitor mode target-arm: respect SCR.FW, SCR.AW and SCTLR.NMFI target-arm: add NSACR register target-arm: add MVBAR support target-arm: add SCTLR_EL3 and make SCTLR banked target-arm: make CSSELR banked target-arm: add TTBR0_EL3 and make TTBR0/1 banked target-arm: add TCR_EL3 and make TTBCR banked target-arm: make c2_mask and c2_base_mask banked target-arm: make DACR banked target-arm: make IFSR banked target-arm: make DFSR banked target-arm: make IFAR/DFAR banked target-arm: make PAR banked target-arm: make c13 cp regs banked (FCSEIDR, ...) target-arm: add cpu feature EL3 to CPUs with Security Extensions Greg Bellows (3): target-arm: rename arm_current_pl to arm_current_el target-arm: add secure state bit to CPREG hash target-arm: make MAIR0/1 banked Sergey Fedorov (3): target-arm: reject switching to monitor mode target-arm: add non-secure Translation Block flag target-arm: add SDER definition hw/arm/pxa2xx.c | 8 +- target-arm/cpu.c | 11 +- target-arm/cpu.h | 518 +++++++++++++++++++++++++++---- target-arm/helper-a64.c | 6 +- target-arm/helper.c | 742 ++++++++++++++++++++++++++++++++++----------- target-arm/internals.h | 9 +- target-arm/machine.c | 8 +- target-arm/op_helper.c | 21 +- target-arm/translate-a64.c | 16 +- target-arm/translate.c | 60 ++-- target-arm/translate.h | 5 +- 11 files changed, 1107 insertions(+), 297 deletions(-) -- 1.8.3.2