From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:35007) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Xccfp-0006rx-ME for qemu-devel@nongnu.org; Fri, 10 Oct 2014 12:04:15 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1Xccfl-00080r-A3 for qemu-devel@nongnu.org; Fri, 10 Oct 2014 12:04:09 -0400 Received: from mail-oi0-f51.google.com ([209.85.218.51]:45107) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Xccfl-00080i-5M for qemu-devel@nongnu.org; Fri, 10 Oct 2014 12:04:05 -0400 Received: by mail-oi0-f51.google.com with SMTP id h136so7040548oig.24 for ; Fri, 10 Oct 2014 09:04:04 -0700 (PDT) From: Greg Bellows Date: Fri, 10 Oct 2014 11:03:21 -0500 Message-Id: <1412957023-11105-11-git-send-email-greg.bellows@linaro.org> In-Reply-To: <1412957023-11105-1-git-send-email-greg.bellows@linaro.org> References: <1412957023-11105-1-git-send-email-greg.bellows@linaro.org> Subject: [Qemu-devel] [PATCH v6 10/32] target-arm: add non-secure Translation Block flag List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org, peter.maydell@linaro.org, serge.fdrv@gmail.com, edgar.iglesias@gmail.com, aggelerf@ethz.ch From: Sergey Fedorov This patch is based on idea found in patch at git://github.com/jowinter/qemu-trustzone.git f3d955c6c0ed8c46bc0eb10b634201032a651dd2 by Johannes Winter . The TBFLAG captures the SCR NS secure state at the time when a TB is created so the correct bank is accessed on system register accesses. It also allows to generate different TCG code depending on CPU secure state. Signed-off-by: Sergey Fedorov Signed-off-by: Fabian Aggeler Signed-off-by: Greg Bellows ========== v5 -> v6 - Removed 64-bit NS TBFLAG macros as they are not needed - Added comment on DisasContext ns field - Replaced use of USE_SECURE_REG with use_secure_reg v4 -> v5 - Merge changes - Fixed issue where TB secure state flag was incorrectly being set based on secure state rather than NS setting. This caused an issue where monitor mode MRC/MCR accesses were always secure rather than being based on NS bit setting. - Added separate 64/32 TB secure state flags - Unconditionalized the setting of the DC ns bit - Removed IS_NS macro and replaced with direct usage. --- target-arm/cpu.h | 7 +++++++ target-arm/translate.c | 1 + target-arm/translate.h | 1 + 3 files changed, 9 insertions(+) diff --git a/target-arm/cpu.h b/target-arm/cpu.h index 9f1613f..59414f3 100644 --- a/target-arm/cpu.h +++ b/target-arm/cpu.h @@ -1546,6 +1546,8 @@ static inline bool arm_singlestep_active(CPUARMState *env) */ #define ARM_TBFLAG_XSCALE_CPAR_SHIFT 20 #define ARM_TBFLAG_XSCALE_CPAR_MASK (3 << ARM_TBFLAG_XSCALE_CPAR_SHIFT) +#define ARM_TBFLAG_NS_SHIFT 22 +#define ARM_TBFLAG_NS_MASK (1 << ARM_TBFLAG_NS_SHIFT) /* Bit usage when in AArch64 state */ #define ARM_TBFLAG_AA64_EL_SHIFT 0 @@ -1590,6 +1592,8 @@ static inline bool arm_singlestep_active(CPUARMState *env) (((F) & ARM_TBFLAG_AA64_SS_ACTIVE_MASK) >> ARM_TBFLAG_AA64_SS_ACTIVE_SHIFT) #define ARM_TBFLAG_AA64_PSTATE_SS(F) \ (((F) & ARM_TBFLAG_AA64_PSTATE_SS_MASK) >> ARM_TBFLAG_AA64_PSTATE_SS_SHIFT) +#define ARM_TBFLAG_NS(F) \ + (((F) & ARM_TBFLAG_NS_MASK) >> ARM_TBFLAG_NS_SHIFT) static inline void cpu_get_tb_cpu_state(CPUARMState *env, target_ulong *pc, target_ulong *cs_base, int *flags) @@ -1639,6 +1643,9 @@ static inline void cpu_get_tb_cpu_state(CPUARMState *env, target_ulong *pc, if (privmode) { *flags |= ARM_TBFLAG_PRIV_MASK; } + if (!(use_secure_reg(env))) { + *flags |= ARM_TBFLAG_NS_MASK; + } if (env->vfp.xregs[ARM_VFP_FPEXC] & (1 << 30) || arm_el_is_aa64(env, 1)) { *flags |= ARM_TBFLAG_VFPEN_MASK; diff --git a/target-arm/translate.c b/target-arm/translate.c index 60655e1..6217dbb 100644 --- a/target-arm/translate.c +++ b/target-arm/translate.c @@ -10958,6 +10958,7 @@ static inline void gen_intermediate_code_internal(ARMCPU *cpu, #if !defined(CONFIG_USER_ONLY) dc->user = (ARM_TBFLAG_PRIV(tb->flags) == 0); #endif + dc->ns = ARM_TBFLAG_NS(tb->flags); dc->cpacr_fpen = ARM_TBFLAG_CPACR_FPEN(tb->flags); dc->vfp_enabled = ARM_TBFLAG_VFPEN(tb->flags); dc->vec_len = ARM_TBFLAG_VECLEN(tb->flags); diff --git a/target-arm/translate.h b/target-arm/translate.h index 2af8f99..519bcc1 100644 --- a/target-arm/translate.h +++ b/target-arm/translate.h @@ -20,6 +20,7 @@ typedef struct DisasContext { #if !defined(CONFIG_USER_ONLY) int user; #endif + bool ns; /* Use non-secure CPREG bank on access */ bool cpacr_fpen; /* FP enabled via CPACR.FPEN */ bool vfp_enabled; /* FP enabled via FPSCR.EN */ int vec_len; -- 1.8.3.2