From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:34886) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Xccfk-0006mX-89 for qemu-devel@nongnu.org; Fri, 10 Oct 2014 12:04:09 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1Xccfc-0007w1-Ez for qemu-devel@nongnu.org; Fri, 10 Oct 2014 12:04:04 -0400 Received: from mail-oi0-f46.google.com ([209.85.218.46]:48333) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Xccfc-0007vo-Aw for qemu-devel@nongnu.org; Fri, 10 Oct 2014 12:03:56 -0400 Received: by mail-oi0-f46.google.com with SMTP id h136so7119273oig.5 for ; Fri, 10 Oct 2014 09:03:55 -0700 (PDT) From: Greg Bellows Date: Fri, 10 Oct 2014 11:03:12 -0500 Message-Id: <1412957023-11105-2-git-send-email-greg.bellows@linaro.org> In-Reply-To: <1412957023-11105-1-git-send-email-greg.bellows@linaro.org> References: <1412957023-11105-1-git-send-email-greg.bellows@linaro.org> Subject: [Qemu-devel] [PATCH v6 01/32] target-arm: increase arrays of registers R13 & R14 List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org, peter.maydell@linaro.org, serge.fdrv@gmail.com, edgar.iglesias@gmail.com, aggelerf@ethz.ch From: Fabian Aggeler Increasing banked_r13 and banked_r14 to store LR_mon and SP_mon (bank index 7). Signed-off-by: Fabian Aggeler Signed-off-by: Greg Bellows ========== v5 -> v6 - Updated vmstate_arm_cpu versioning from 20 to 21 --- target-arm/cpu.h | 4 ++-- target-arm/machine.c | 8 ++++---- 2 files changed, 6 insertions(+), 6 deletions(-) diff --git a/target-arm/cpu.h b/target-arm/cpu.h index 65a3417..81fffd2 100644 --- a/target-arm/cpu.h +++ b/target-arm/cpu.h @@ -153,8 +153,8 @@ typedef struct CPUARMState { /* Banked registers. */ uint64_t banked_spsr[8]; - uint32_t banked_r13[6]; - uint32_t banked_r14[6]; + uint32_t banked_r13[8]; + uint32_t banked_r14[8]; /* These hold r8-r12. */ uint32_t usr_regs[5]; diff --git a/target-arm/machine.c b/target-arm/machine.c index ddb7d05..f1c903d 100644 --- a/target-arm/machine.c +++ b/target-arm/machine.c @@ -222,8 +222,8 @@ static int cpu_post_load(void *opaque, int version_id) const VMStateDescription vmstate_arm_cpu = { .name = "cpu", - .version_id = 20, - .minimum_version_id = 20, + .version_id = 21, + .minimum_version_id = 21, .pre_save = cpu_pre_save, .post_load = cpu_post_load, .fields = (VMStateField[]) { @@ -238,8 +238,8 @@ const VMStateDescription vmstate_arm_cpu = { }, VMSTATE_UINT32(env.spsr, ARMCPU), VMSTATE_UINT64_ARRAY(env.banked_spsr, ARMCPU, 8), - VMSTATE_UINT32_ARRAY(env.banked_r13, ARMCPU, 6), - VMSTATE_UINT32_ARRAY(env.banked_r14, ARMCPU, 6), + VMSTATE_UINT32_ARRAY(env.banked_r13, ARMCPU, 8), + VMSTATE_UINT32_ARRAY(env.banked_r14, ARMCPU, 8), VMSTATE_UINT32_ARRAY(env.usr_regs, ARMCPU, 5), VMSTATE_UINT32_ARRAY(env.fiq_regs, ARMCPU, 5), VMSTATE_UINT64_ARRAY(env.elr_el, ARMCPU, 4), -- 1.8.3.2