From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:35321) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1XccgC-0007Xu-Bm for qemu-devel@nongnu.org; Fri, 10 Oct 2014 12:04:38 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1Xccg6-0008BU-NW for qemu-devel@nongnu.org; Fri, 10 Oct 2014 12:04:32 -0400 Received: from mail-oi0-f47.google.com ([209.85.218.47]:52164) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Xccg6-0008BO-IN for qemu-devel@nongnu.org; Fri, 10 Oct 2014 12:04:26 -0400 Received: by mail-oi0-f47.google.com with SMTP id a141so7291201oig.20 for ; Fri, 10 Oct 2014 09:04:26 -0700 (PDT) From: Greg Bellows Date: Fri, 10 Oct 2014 11:03:43 -0500 Message-Id: <1412957023-11105-33-git-send-email-greg.bellows@linaro.org> In-Reply-To: <1412957023-11105-1-git-send-email-greg.bellows@linaro.org> References: <1412957023-11105-1-git-send-email-greg.bellows@linaro.org> Subject: [Qemu-devel] [PATCH v6 32/32] target-arm: add cpu feature EL3 to CPUs with Security Extensions List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org, peter.maydell@linaro.org, serge.fdrv@gmail.com, edgar.iglesias@gmail.com, aggelerf@ethz.ch From: Fabian Aggeler Set ARM_FEATURE_EL3 feature for CPUs that implement Security Extensions. Signed-off-by: Fabian Aggeler Signed-off-by: Greg Bellows --- target-arm/cpu.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/target-arm/cpu.c b/target-arm/cpu.c index 8ba72ed..fa12602 100644 --- a/target-arm/cpu.c +++ b/target-arm/cpu.c @@ -601,6 +601,7 @@ static void arm1176_initfn(Object *obj) set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS); set_feature(&cpu->env, ARM_FEATURE_CACHE_DIRTY_REG); set_feature(&cpu->env, ARM_FEATURE_CACHE_BLOCK_OPS); + set_feature(&cpu->env, ARM_FEATURE_EL3); cpu->midr = 0x410fb767; cpu->reset_fpsid = 0x410120b5; cpu->mvfr0 = 0x11111111; @@ -687,6 +688,7 @@ static void cortex_a8_initfn(Object *obj) set_feature(&cpu->env, ARM_FEATURE_NEON); set_feature(&cpu->env, ARM_FEATURE_THUMB2EE); set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS); + set_feature(&cpu->env, ARM_FEATURE_EL3); cpu->midr = 0x410fc080; cpu->reset_fpsid = 0x410330c0; cpu->mvfr0 = 0x11110222; @@ -754,6 +756,7 @@ static void cortex_a9_initfn(Object *obj) set_feature(&cpu->env, ARM_FEATURE_VFP_FP16); set_feature(&cpu->env, ARM_FEATURE_NEON); set_feature(&cpu->env, ARM_FEATURE_THUMB2EE); + set_feature(&cpu->env, ARM_FEATURE_EL3); /* Note that A9 supports the MP extensions even for * A9UP and single-core A9MP (which are both different * and valid configurations; we don't model A9UP). @@ -821,6 +824,7 @@ static void cortex_a15_initfn(Object *obj) set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS); set_feature(&cpu->env, ARM_FEATURE_CBAR_RO); set_feature(&cpu->env, ARM_FEATURE_LPAE); + set_feature(&cpu->env, ARM_FEATURE_EL3); cpu->kvm_target = QEMU_KVM_ARM_TARGET_CORTEX_A15; cpu->midr = 0x412fc0f1; cpu->reset_fpsid = 0x410430f0; -- 1.8.3.2