qemu-devel.nongnu.org archive mirror
 help / color / mirror / Atom feed
From: Greg Bellows <greg.bellows@linaro.org>
To: qemu-devel@nongnu.org, peter.maydell@linaro.org,
	serge.fdrv@gmail.com, edgar.iglesias@gmail.com, aggelerf@ethz.ch
Subject: [Qemu-devel] [PATCH v6 03/32] target-arm: reject switching to monitor mode
Date: Fri, 10 Oct 2014 11:03:14 -0500	[thread overview]
Message-ID: <1412957023-11105-4-git-send-email-greg.bellows@linaro.org> (raw)
In-Reply-To: <1412957023-11105-1-git-send-email-greg.bellows@linaro.org>

From: Sergey Fedorov <s.fedorov@samsung.com>

Reject switching to monitor mode from non-secure state.

Signed-off-by: Sergey Fedorov <s.fedorov@samsung.com>
Signed-off-by: Fabian Aggeler <aggelerf@ethz.ch>
Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
Signed-off-by: Greg Bellows <greg.bellows@linaro.org>
---
 target-arm/helper.c | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/target-arm/helper.c b/target-arm/helper.c
index 2669e15..d6e3b52 100644
--- a/target-arm/helper.c
+++ b/target-arm/helper.c
@@ -3531,6 +3531,8 @@ static int bad_mode_switch(CPUARMState *env, int mode)
     case ARM_CPU_MODE_IRQ:
     case ARM_CPU_MODE_FIQ:
         return 0;
+    case ARM_CPU_MODE_MON:
+        return !arm_is_secure(env);
     default:
         return 1;
     }
-- 
1.8.3.2

  parent reply	other threads:[~2014-10-10 16:04 UTC|newest]

Thread overview: 50+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2014-10-10 16:03 [Qemu-devel] [PATCH v6 00/32] target-arm: add Security Extensions for CPUs Greg Bellows
2014-10-10 16:03 ` [Qemu-devel] [PATCH v6 01/32] target-arm: increase arrays of registers R13 & R14 Greg Bellows
2014-10-13 12:31   ` Peter Maydell
2014-10-10 16:03 ` [Qemu-devel] [PATCH v6 02/32] target-arm: add arm_is_secure() function Greg Bellows
2014-10-13 12:41   ` Peter Maydell
2014-10-10 16:03 ` Greg Bellows [this message]
2014-10-13 12:58   ` [Qemu-devel] [PATCH v6 03/32] target-arm: reject switching to monitor mode Peter Maydell
2014-10-10 16:03 ` [Qemu-devel] [PATCH v6 04/32] target-arm: rename arm_current_pl to arm_current_el Greg Bellows
2014-10-13 13:00   ` Peter Maydell
2014-10-10 16:03 ` [Qemu-devel] [PATCH v6 05/32] target-arm: make arm_current_el() return EL3 Greg Bellows
2014-10-13 13:04   ` Peter Maydell
2014-10-10 16:03 ` [Qemu-devel] [PATCH v6 06/32] target-arm: A32: Emulate the SMC instruction Greg Bellows
2014-10-13 13:06   ` Peter Maydell
2014-10-13 13:13     ` Greg Bellows
2014-10-13 13:36       ` Peter Maydell
2014-10-13 13:56         ` Greg Bellows
2014-10-10 16:03 ` [Qemu-devel] [PATCH v6 07/32] target-arm: extend async excp masking Greg Bellows
2014-10-10 16:03 ` [Qemu-devel] [PATCH v6 08/32] target-arm: add async excp target_el function Greg Bellows
2014-10-10 16:03 ` [Qemu-devel] [PATCH v6 09/32] target-arm: add banked register accessors Greg Bellows
2014-10-10 16:03 ` [Qemu-devel] [PATCH v6 10/32] target-arm: add non-secure Translation Block flag Greg Bellows
2014-10-10 16:03 ` [Qemu-devel] [PATCH v6 11/32] target-arm: add CPREG secure state support Greg Bellows
2014-10-17  1:32   ` Edgar E. Iglesias
2014-10-17 13:37     ` Greg Bellows
2014-10-17 15:20       ` Greg Bellows
2014-10-17 15:27         ` Laurent Desnogues
2014-10-17 15:30           ` Greg Bellows
2014-10-17 19:12         ` Greg Bellows
2014-10-10 16:03 ` [Qemu-devel] [PATCH v6 12/32] target-arm: add secure state bit to CPREG hash Greg Bellows
2014-10-10 16:03 ` [Qemu-devel] [PATCH v6 13/32] target-arm: insert AArch32 cpregs twice into hashtable Greg Bellows
2014-10-10 16:03 ` [Qemu-devel] [PATCH v6 14/32] target-arm: move AArch32 SCR into security reglist Greg Bellows
2014-10-10 16:03 ` [Qemu-devel] [PATCH v6 15/32] target-arm: implement IRQ/FIQ routing to Monitor mode Greg Bellows
2014-10-10 16:03 ` [Qemu-devel] [PATCH v6 16/32] target-arm: respect SCR.FW, SCR.AW and SCTLR.NMFI Greg Bellows
2014-10-10 16:03 ` [Qemu-devel] [PATCH v6 17/32] target-arm: add NSACR register Greg Bellows
2014-10-10 16:03 ` [Qemu-devel] [PATCH v6 18/32] target-arm: add SDER definition Greg Bellows
2014-10-10 16:03 ` [Qemu-devel] [PATCH v6 19/32] target-arm: add MVBAR support Greg Bellows
2014-10-10 16:03 ` [Qemu-devel] [PATCH v6 20/32] target-arm: add SCTLR_EL3 and make SCTLR banked Greg Bellows
2014-10-10 16:03 ` [Qemu-devel] [PATCH v6 21/32] target-arm: make CSSELR banked Greg Bellows
2014-10-10 16:03 ` [Qemu-devel] [PATCH v6 22/32] target-arm: add TTBR0_EL3 and make TTBR0/1 banked Greg Bellows
2014-10-10 16:03 ` [Qemu-devel] [PATCH v6 23/32] target-arm: add TCR_EL3 and make TTBCR banked Greg Bellows
2014-10-10 16:03 ` [Qemu-devel] [PATCH v6 24/32] target-arm: make c2_mask and c2_base_mask banked Greg Bellows
2014-10-10 16:03 ` [Qemu-devel] [PATCH v6 25/32] target-arm: make DACR banked Greg Bellows
2014-10-10 16:03 ` [Qemu-devel] [PATCH v6 26/32] target-arm: make IFSR banked Greg Bellows
2014-10-10 16:03 ` [Qemu-devel] [PATCH v6 27/32] target-arm: make DFSR banked Greg Bellows
2014-10-10 16:03 ` [Qemu-devel] [PATCH v6 28/32] target-arm: make IFAR/DFAR banked Greg Bellows
2014-10-10 16:03 ` [Qemu-devel] [PATCH v6 29/32] target-arm: make PAR banked Greg Bellows
2014-10-10 16:03 ` [Qemu-devel] [PATCH v6 30/32] target-arm: make c13 cp regs banked (FCSEIDR, ...) Greg Bellows
2014-10-15  3:17   ` Edgar E. Iglesias
2014-10-16 18:20     ` Greg Bellows
2014-10-10 16:03 ` [Qemu-devel] [PATCH v6 31/32] target-arm: make MAIR0/1 banked Greg Bellows
2014-10-10 16:03 ` [Qemu-devel] [PATCH v6 32/32] target-arm: add cpu feature EL3 to CPUs with Security Extensions Greg Bellows

Reply instructions:

You may reply publicly to this message via plain-text email
using any one of the following methods:

* Save the following mbox file, import it into your mail client,
  and reply-to-all from there: mbox

  Avoid top-posting and favor interleaved quoting:
  https://en.wikipedia.org/wiki/Posting_style#Interleaved_style

* Reply using the --to, --cc, and --in-reply-to
  switches of git-send-email(1):

  git send-email \
    --in-reply-to=1412957023-11105-4-git-send-email-greg.bellows@linaro.org \
    --to=greg.bellows@linaro.org \
    --cc=aggelerf@ethz.ch \
    --cc=edgar.iglesias@gmail.com \
    --cc=peter.maydell@linaro.org \
    --cc=qemu-devel@nongnu.org \
    --cc=serge.fdrv@gmail.com \
    /path/to/YOUR_REPLY

  https://kernel.org/pub/software/scm/git/docs/git-send-email.html

* If your mail client supports setting the In-Reply-To header
  via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).