From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:34628) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1XdhWr-00028E-B5 for qemu-devel@nongnu.org; Mon, 13 Oct 2014 11:27:27 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1XdhWl-0001zk-6l for qemu-devel@nongnu.org; Mon, 13 Oct 2014 11:27:21 -0400 Received: from mail.uni-paderborn.de ([131.234.142.9]:34355) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1XdhWk-0001zV-Vj for qemu-devel@nongnu.org; Mon, 13 Oct 2014 11:27:15 -0400 From: Bastian Koppelmann Date: Mon, 13 Oct 2014 17:26:59 +0100 Message-Id: <1413217624-14415-1-git-send-email-kbastian@mail.uni-paderborn.de> Subject: [Qemu-devel] [PATCH v3 0/5] Add TriCore ABS, ABSB, B, BIT, BO instructions List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org Cc: peter.maydell@linaro.org, rth@twiddle.net Hi guys, here is the next round of TriCore patches. The first patch addresses a clang issue mentioned by Peter Maydell and some bugfixes. And the other four add instructions of the ABS, ABSB, B, BIT and BO opcode format. Thanks, Bastian v2 -> v3: - OR_NOR_T, AND_NOR_T: Now uses normal conditionals instead of preprocessor. - Add microcode generator functions gen_st/ld_preincr, which write back the address after the memory access. - ST/LD_PREINC insn now use gen_st/ld_preincr or write back the address after after the memory access. Bastian Koppelmann (5): target-tricore: Cleanup and Bugfixes target-tricore: Add instructions of ABS, ABSB opcode format target-tricore: Add instructions of B opcode format target-tricore: Add instructions of BIT opcode format target-tricore: Add instructions of BO opcode format target-tricore/helper.h | 7 + target-tricore/op_helper.c | 128 +++- target-tricore/translate.c | 1305 ++++++++++++++++++++++++++++++++++++++ target-tricore/tricore-opcodes.h | 4 +- 4 files changed, 1417 insertions(+), 27 deletions(-) -- 2.1.2