From: Leon Alrae <leon.alrae@imgtec.com>
To: qemu-devel@nongnu.org
Subject: [Qemu-devel] [PULL 20/28] mips_malta: update malta's pseudo-bootloader - replace JR with JALR
Date: Wed, 15 Oct 2014 10:54:12 +0100 [thread overview]
Message-ID: <1413366860-7833-21-git-send-email-leon.alrae@imgtec.com> (raw)
In-Reply-To: <1413366860-7833-1-git-send-email-leon.alrae@imgtec.com>
JR has been removed in R6 and now this instruction will cause Reserved
Instruction Exception. Therefore use JALR with rd=0 which is equivalent to JR.
Signed-off-by: Leon Alrae <leon.alrae@imgtec.com>
Reviewed-by: Aurelien Jarno <aurelien@aurel32.net>
---
hw/mips/mips_malta.c | 10 +++++-----
1 file changed, 5 insertions(+), 5 deletions(-)
diff --git a/hw/mips/mips_malta.c b/hw/mips/mips_malta.c
index b20807c..e8e075c 100644
--- a/hw/mips/mips_malta.c
+++ b/hw/mips/mips_malta.c
@@ -697,12 +697,12 @@ static void write_bootloader (CPUMIPSState *env, uint8_t *base,
/* Jump to kernel code */
stl_p(p++, 0x3c1f0000 | ((kernel_entry >> 16) & 0xffff)); /* lui ra, high(kernel_entry) */
stl_p(p++, 0x37ff0000 | (kernel_entry & 0xffff)); /* ori ra, ra, low(kernel_entry) */
- stl_p(p++, 0x03e00008); /* jr ra */
+ stl_p(p++, 0x03e00009); /* jalr ra */
stl_p(p++, 0x00000000); /* nop */
/* YAMON subroutines */
p = (uint32_t *) (base + 0x800);
- stl_p(p++, 0x03e00008); /* jr ra */
+ stl_p(p++, 0x03e00009); /* jalr ra */
stl_p(p++, 0x24020000); /* li v0,0 */
/* 808 YAMON print */
stl_p(p++, 0x03e06821); /* move t5,ra */
@@ -716,7 +716,7 @@ static void write_bootloader (CPUMIPSState *env, uint8_t *base,
stl_p(p++, 0x00000000); /* nop */
stl_p(p++, 0x08000205); /* j 814 */
stl_p(p++, 0x00000000); /* nop */
- stl_p(p++, 0x01a00008); /* jr t5 */
+ stl_p(p++, 0x01a00009); /* jalr t5 */
stl_p(p++, 0x01602021); /* move a0,t3 */
/* 0x83c YAMON print_count */
stl_p(p++, 0x03e06821); /* move t5,ra */
@@ -730,7 +730,7 @@ static void write_bootloader (CPUMIPSState *env, uint8_t *base,
stl_p(p++, 0x258cffff); /* addiu t4,t4,-1 */
stl_p(p++, 0x1580fffa); /* bnez t4,84c */
stl_p(p++, 0x00000000); /* nop */
- stl_p(p++, 0x01a00008); /* jr t5 */
+ stl_p(p++, 0x01a00009); /* jalr t5 */
stl_p(p++, 0x01602021); /* move a0,t3 */
/* 0x870 */
stl_p(p++, 0x3c08b800); /* lui t0,0xb400 */
@@ -740,7 +740,7 @@ static void write_bootloader (CPUMIPSState *env, uint8_t *base,
stl_p(p++, 0x31290040); /* andi t1,t1,0x40 */
stl_p(p++, 0x1120fffc); /* beqz t1,878 <outch+0x8> */
stl_p(p++, 0x00000000); /* nop */
- stl_p(p++, 0x03e00008); /* jr ra */
+ stl_p(p++, 0x03e00009); /* jalr ra */
stl_p(p++, 0xa1040000); /* sb a0,0(t0) */
}
--
2.1.0
next prev parent reply other threads:[~2014-10-15 9:55 UTC|newest]
Thread overview: 34+ messages / expand[flat|nested] mbox.gz Atom feed top
2014-10-15 9:53 [Qemu-devel] [PULL 00/28] target-mips queue Leon Alrae
2014-10-15 9:53 ` [Qemu-devel] [PULL 01/28] target-mips: define ISA_MIPS64R6 Leon Alrae
2014-10-15 9:53 ` [Qemu-devel] [PULL 02/28] target-mips: signal RI Exception on instructions removed in R6 Leon Alrae
2014-10-15 9:53 ` [Qemu-devel] [PULL 03/28] target-mips: add SELEQZ and SELNEZ instructions Leon Alrae
2014-10-15 9:53 ` [Qemu-devel] [PULL 04/28] target-mips: move LL and SC instructions Leon Alrae
2014-10-15 9:53 ` [Qemu-devel] [PULL 05/28] target-mips: extract decode_opc_special* from decode_opc Leon Alrae
2014-10-15 9:53 ` [Qemu-devel] [PULL 06/28] target-mips: split decode_opc_special* into *_r6 and *_legacy Leon Alrae
2014-10-15 9:53 ` [Qemu-devel] [PULL 07/28] target-mips: signal RI Exception on DSP and Loongson instructions Leon Alrae
2014-10-15 9:54 ` [Qemu-devel] [PULL 08/28] target-mips: move PREF, CACHE, LLD and SCD instructions Leon Alrae
2014-10-15 9:54 ` [Qemu-devel] [PULL 09/28] target-mips: redefine Integer Multiply and Divide instructions Leon Alrae
2014-10-15 9:54 ` [Qemu-devel] [PULL 10/28] target-mips: move CLO, DCLO, CLZ, DCLZ, SDBBP and free special2 in R6 Leon Alrae
2014-10-15 9:54 ` [Qemu-devel] [PULL 11/28] target-mips: Status.UX/SX/KX enable 32-bit address wrapping Leon Alrae
2014-10-15 9:54 ` [Qemu-devel] [PULL 12/28] target-mips: add ALIGN, DALIGN, BITSWAP and DBITSWAP instructions Leon Alrae
2014-10-15 9:54 ` [Qemu-devel] [PULL 13/28] target-mips: add compact and CP1 branches Leon Alrae
2014-10-15 9:54 ` [Qemu-devel] [PULL 14/28] target-mips: add AUI, LSA and PCREL instruction families Leon Alrae
2014-10-15 9:54 ` [Qemu-devel] [PULL 15/28] softfloat: add functions corresponding to IEEE-2008 min/maxNumMag Leon Alrae
2014-10-15 9:54 ` [Qemu-devel] [PULL 16/28] target-mips: add new Floating Point instructions Leon Alrae
2014-10-15 9:54 ` [Qemu-devel] [PULL 17/28] target-mips: add new Floating Point Comparison instructions Leon Alrae
2014-10-15 9:54 ` [Qemu-devel] [PULL 18/28] target-mips: do not allow Status.FR=0 mode in 64-bit FPU Leon Alrae
2014-10-15 9:54 ` [Qemu-devel] [PULL 19/28] target-mips: remove JR, BLTZAL, BGEZAL and add NAL, BAL instructions Leon Alrae
2014-10-15 9:54 ` Leon Alrae [this message]
2014-10-15 9:54 ` [Qemu-devel] [PULL 21/28] target-mips: define a new generic CPU supporting MIPS64 Release 6 ISA Leon Alrae
2014-10-15 9:54 ` [Qemu-devel] [PULL 22/28] target-mips/translate.c: Update OPC_SYNCI Leon Alrae
2014-10-15 9:54 ` [Qemu-devel] [PULL 23/28] target-mips: fix broken MIPS16 and microMIPS Leon Alrae
2014-10-15 9:54 ` [Qemu-devel] [PULL 24/28] target-mips/dsp_helper.c: Remove unused function get_DSPControl_24() Leon Alrae
2014-10-15 9:54 ` [Qemu-devel] [PULL 25/28] target-mips/op_helper.c: Remove unused do_lbu() function Leon Alrae
2014-10-15 9:54 ` [Qemu-devel] [PULL 26/28] target-mips/translate.c: Add ifdef guard around check_mips64() Leon Alrae
2014-10-15 9:54 ` [Qemu-devel] [PULL 27/28] target-mips/dsp_helper.c: Add ifdef guards around various functions Leon Alrae
2014-10-15 9:54 ` [Qemu-devel] [PULL 28/28] target-mips: Remove unused gen_load_ACX, gen_store_ACX and cpu_ACX Leon Alrae
2014-10-16 9:49 ` [Qemu-devel] [PULL 00/28] target-mips queue Peter Maydell
2014-10-16 9:59 ` Leon Alrae
2014-10-22 12:08 ` Peter Maydell
2014-10-22 12:22 ` Peter Maydell
2014-10-22 12:32 ` Leon Alrae
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=1413366860-7833-21-git-send-email-leon.alrae@imgtec.com \
--to=leon.alrae@imgtec.com \
--cc=qemu-devel@nongnu.org \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).