From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:42092) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1XgcjD-0006ns-Ve for qemu-devel@nongnu.org; Tue, 21 Oct 2014 12:56:16 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1Xgcj9-0006sw-1S for qemu-devel@nongnu.org; Tue, 21 Oct 2014 12:56:11 -0400 Received: from mail-qg0-f41.google.com ([209.85.192.41]:35789) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Xgcj8-0006sg-SL for qemu-devel@nongnu.org; Tue, 21 Oct 2014 12:56:06 -0400 Received: by mail-qg0-f41.google.com with SMTP id a108so1203533qge.28 for ; Tue, 21 Oct 2014 09:56:06 -0700 (PDT) From: Greg Bellows Date: Tue, 21 Oct 2014 11:55:27 -0500 Message-Id: <1413910544-20150-16-git-send-email-greg.bellows@linaro.org> In-Reply-To: <1413910544-20150-1-git-send-email-greg.bellows@linaro.org> References: <1413910544-20150-1-git-send-email-greg.bellows@linaro.org> Subject: [Qemu-devel] [PATCH v7 15/32] target-arm: implement IRQ/FIQ routing to Monitor mode List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org, peter.maydell@linaro.org, serge.fdrv@gmail.com, edgar.iglesias@gmail.com, aggelerf@ethz.ch Cc: greg.bellows@linaro.org From: Fabian Aggeler SCR.{IRQ/FIQ} bits allow to route IRQ/FIQ exceptions to monitor CPU mode. When taking IRQ exception to monitor mode FIQ exception is additionally masked. Signed-off-by: Sergey Fedorov Signed-off-by: Fabian Aggeler Signed-off-by: Greg Bellows --- target-arm/helper.c | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/target-arm/helper.c b/target-arm/helper.c index bc82951..a22fcb2 100644 --- a/target-arm/helper.c +++ b/target-arm/helper.c @@ -4212,12 +4212,21 @@ void arm_cpu_do_interrupt(CPUState *cs) /* Disable IRQ and imprecise data aborts. */ mask = CPSR_A | CPSR_I; offset = 4; + if (env->cp15.scr_el3 & SCR_IRQ) { + /* IRQ routed to monitor mode */ + new_mode = ARM_CPU_MODE_MON; + mask |= CPSR_F; + } break; case EXCP_FIQ: new_mode = ARM_CPU_MODE_FIQ; addr = 0x1c; /* Disable FIQ, IRQ and imprecise data aborts. */ mask = CPSR_A | CPSR_I | CPSR_F; + if (env->cp15.scr_el3 & SCR_FIQ) { + /* FIQ routed to monitor mode */ + new_mode = ARM_CPU_MODE_MON; + } offset = 4; break; case EXCP_SMC: -- 1.8.3.2