From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:42168) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1XgcjJ-0006x3-G6 for qemu-devel@nongnu.org; Tue, 21 Oct 2014 12:56:22 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1XgcjD-0006vv-45 for qemu-devel@nongnu.org; Tue, 21 Oct 2014 12:56:17 -0400 Received: from mail-qg0-f43.google.com ([209.85.192.43]:63749) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1XgcjD-0006vl-0J for qemu-devel@nongnu.org; Tue, 21 Oct 2014 12:56:11 -0400 Received: by mail-qg0-f43.google.com with SMTP id j107so1185949qga.2 for ; Tue, 21 Oct 2014 09:56:10 -0700 (PDT) From: Greg Bellows Date: Tue, 21 Oct 2014 11:55:33 -0500 Message-Id: <1413910544-20150-22-git-send-email-greg.bellows@linaro.org> In-Reply-To: <1413910544-20150-1-git-send-email-greg.bellows@linaro.org> References: <1413910544-20150-1-git-send-email-greg.bellows@linaro.org> Subject: [Qemu-devel] [PATCH v7 21/32] target-arm: make CSSELR banked List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org, peter.maydell@linaro.org, serge.fdrv@gmail.com, edgar.iglesias@gmail.com, aggelerf@ethz.ch Cc: greg.bellows@linaro.org From: Fabian Aggeler Rename CSSELR (cache size selection register) and add secure instance (AArch32). Signed-off-by: Fabian Aggeler Signed-off-by: Greg Bellows ========== v5 -> v6 - Changed _el field variants to be array based - Switch to use distinct CPREG secure flags. - Merged CSSELR and CSSELR_EL1 reginfo entries v4 -> v5 - Changed to use the CCSIDR cpreg bank flag to select the csselr bank instead of the A32_BANKED macro. This more accurately uses the secure state bank matching the CCSIDR. Signed-off-by: Greg Bellows --- target-arm/cpu.h | 10 +++++++++- target-arm/helper.c | 16 ++++++++++++---- 2 files changed, 21 insertions(+), 5 deletions(-) diff --git a/target-arm/cpu.h b/target-arm/cpu.h index a46ab7b..8b98c62 100644 --- a/target-arm/cpu.h +++ b/target-arm/cpu.h @@ -177,7 +177,15 @@ typedef struct CPUARMState { /* System control coprocessor (cp15) */ struct { uint32_t c0_cpuid; - uint64_t c0_cssel; /* Cache size selection. */ + union { /* Cache size selection */ + struct { + uint64_t _unused_csselr0; + uint64_t csselr_ns; + uint64_t _unused_csselr1; + uint64_t csselr_s; + }; + uint64_t csselr_el[4]; + }; union { /* System control register. */ struct { uint64_t _unused_sctlr; diff --git a/target-arm/helper.c b/target-arm/helper.c index 6a7c112..a8fe482 100644 --- a/target-arm/helper.c +++ b/target-arm/helper.c @@ -789,7 +789,14 @@ static void scr_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value) static uint64_t ccsidr_read(CPUARMState *env, const ARMCPRegInfo *ri) { ARMCPU *cpu = arm_env_get_cpu(env); - return cpu->ccsidr[env->cp15.c0_cssel]; + + /* Acquire the CSSELR index from the bank corresponding to the CCSIDR + * bank + */ + uint32_t index = A32_BANKED_REG_GET(env, csselr, + ARM_CP_SECSTATE_TEST(ri, ARM_CP_SECSTATE_S)); + + return cpu->ccsidr[index]; } static void csselr_write(CPUARMState *env, const ARMCPRegInfo *ri, @@ -915,9 +922,10 @@ static const ARMCPRegInfo v7_cp_reginfo[] = { .opc0 = 3, .crn = 0, .crm = 0, .opc1 = 1, .opc2 = 0, .access = PL1_R, .readfn = ccsidr_read, .type = ARM_CP_NO_MIGRATE }, { .name = "CSSELR", .state = ARM_CP_STATE_BOTH, - .opc0 = 3, .crn = 0, .crm = 0, .opc1 = 2, .opc2 = 0, - .access = PL1_RW, .fieldoffset = offsetof(CPUARMState, cp15.c0_cssel), - .writefn = csselr_write, .resetvalue = 0 }, + .cp = 15, .crn = 0, .crm = 0, .opc1 = 2, .opc2 = 0, + .access = PL1_RW, .writefn = csselr_write, .resetvalue = 0, + .bank_fieldoffsets = { offsetof(CPUARMState, cp15.csselr_s), + offsetof(CPUARMState, cp15.csselr_ns) } }, /* Auxiliary ID register: this actually has an IMPDEF value but for now * just RAZ for all cores: */ -- 1.8.3.2