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From: Greg Bellows <greg.bellows@linaro.org>
To: qemu-devel@nongnu.org, peter.maydell@linaro.org,
	serge.fdrv@gmail.com, edgar.iglesias@gmail.com, aggelerf@ethz.ch
Cc: greg.bellows@linaro.org
Subject: [Qemu-devel] [PATCH v7 32/32] target-arm: add cpu feature EL3 to CPUs with Security Extensions
Date: Tue, 21 Oct 2014 11:55:44 -0500	[thread overview]
Message-ID: <1413910544-20150-33-git-send-email-greg.bellows@linaro.org> (raw)
In-Reply-To: <1413910544-20150-1-git-send-email-greg.bellows@linaro.org>

From: Fabian Aggeler <aggelerf@ethz.ch>

Set ARM_FEATURE_EL3 feature for CPUs that implement Security Extensions.

Signed-off-by: Fabian Aggeler <aggelerf@ethz.ch>
Signed-off-by: Greg Bellows <greg.bellows@linaro.org>
---
 target-arm/cpu.c | 4 ++++
 1 file changed, 4 insertions(+)

diff --git a/target-arm/cpu.c b/target-arm/cpu.c
index 63573c6..1e93d7e 100644
--- a/target-arm/cpu.c
+++ b/target-arm/cpu.c
@@ -610,6 +610,7 @@ static void arm1176_initfn(Object *obj)
     set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
     set_feature(&cpu->env, ARM_FEATURE_CACHE_DIRTY_REG);
     set_feature(&cpu->env, ARM_FEATURE_CACHE_BLOCK_OPS);
+    set_feature(&cpu->env, ARM_FEATURE_EL3);
     cpu->midr = 0x410fb767;
     cpu->reset_fpsid = 0x410120b5;
     cpu->mvfr0 = 0x11111111;
@@ -696,6 +697,7 @@ static void cortex_a8_initfn(Object *obj)
     set_feature(&cpu->env, ARM_FEATURE_NEON);
     set_feature(&cpu->env, ARM_FEATURE_THUMB2EE);
     set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
+    set_feature(&cpu->env, ARM_FEATURE_EL3);
     cpu->midr = 0x410fc080;
     cpu->reset_fpsid = 0x410330c0;
     cpu->mvfr0 = 0x11110222;
@@ -763,6 +765,7 @@ static void cortex_a9_initfn(Object *obj)
     set_feature(&cpu->env, ARM_FEATURE_VFP_FP16);
     set_feature(&cpu->env, ARM_FEATURE_NEON);
     set_feature(&cpu->env, ARM_FEATURE_THUMB2EE);
+    set_feature(&cpu->env, ARM_FEATURE_EL3);
     /* Note that A9 supports the MP extensions even for
      * A9UP and single-core A9MP (which are both different
      * and valid configurations; we don't model A9UP).
@@ -830,6 +833,7 @@ static void cortex_a15_initfn(Object *obj)
     set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
     set_feature(&cpu->env, ARM_FEATURE_CBAR_RO);
     set_feature(&cpu->env, ARM_FEATURE_LPAE);
+    set_feature(&cpu->env, ARM_FEATURE_EL3);
     cpu->kvm_target = QEMU_KVM_ARM_TARGET_CORTEX_A15;
     cpu->midr = 0x412fc0f1;
     cpu->reset_fpsid = 0x410430f0;
-- 
1.8.3.2

  parent reply	other threads:[~2014-10-21 16:56 UTC|newest]

Thread overview: 53+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2014-10-21 16:55 [Qemu-devel] [PATCH v7 00/32] target-arm: add Security Extensions for CPUs Greg Bellows
2014-10-21 16:55 ` [Qemu-devel] [PATCH v7 01/32] target-arm: increase arrays of registers R13 & R14 Greg Bellows
2014-10-21 16:55 ` [Qemu-devel] [PATCH v7 02/32] target-arm: add arm_is_secure() function Greg Bellows
2014-10-21 16:55 ` [Qemu-devel] [PATCH v7 03/32] target-arm: reject switching to monitor mode Greg Bellows
2014-10-21 16:55 ` [Qemu-devel] [PATCH v7 04/32] target-arm: rename arm_current_pl to arm_current_el Greg Bellows
2014-10-23 14:53   ` Peter Maydell
2014-10-21 16:55 ` [Qemu-devel] [PATCH v7 05/32] target-arm: make arm_current_el() return EL3 Greg Bellows
2015-01-16 18:36   ` Peter Maydell
2015-01-19 13:22     ` Peter Maydell
2015-01-19 17:44       ` Richard Henderson
2015-01-19 19:00         ` Peter Maydell
2015-01-19 19:30           ` Richard Henderson
2015-01-19 22:54             ` Edgar E. Iglesias
2014-10-21 16:55 ` [Qemu-devel] [PATCH v7 06/32] target-arm: A32: Emulate the SMC instruction Greg Bellows
2014-10-23 14:06   ` Peter Maydell
2014-10-21 16:55 ` [Qemu-devel] [PATCH v7 07/32] target-arm: extend async excp masking Greg Bellows
2014-10-24 16:25   ` Peter Maydell
2014-10-24 22:43     ` Greg Bellows
2014-10-26 22:30       ` Peter Maydell
2014-10-27 11:57         ` Peter Maydell
2014-10-27 15:59           ` Greg Bellows
2014-10-21 16:55 ` [Qemu-devel] [PATCH v7 08/32] target-arm: add async excp target_el function Greg Bellows
2014-10-24 16:26   ` Peter Maydell
2014-10-28 14:50     ` Greg Bellows
2014-10-21 16:55 ` [Qemu-devel] [PATCH v7 09/32] target-arm: add banked register accessors Greg Bellows
2014-10-24 16:37   ` Peter Maydell
2014-10-28 18:42     ` Greg Bellows
2014-10-21 16:55 ` [Qemu-devel] [PATCH v7 10/32] target-arm: add non-secure Translation Block flag Greg Bellows
2014-10-24 16:40   ` Peter Maydell
2014-10-28 15:21     ` Greg Bellows
2014-10-21 16:55 ` [Qemu-devel] [PATCH v7 11/32] target-arm: add CPREG secure state support Greg Bellows
2014-10-21 16:55 ` [Qemu-devel] [PATCH v7 12/32] target-arm: add secure state bit to CPREG hash Greg Bellows
2014-10-21 16:55 ` [Qemu-devel] [PATCH v7 13/32] target-arm: insert AArch32 cpregs twice into hashtable Greg Bellows
2014-10-21 16:55 ` [Qemu-devel] [PATCH v7 14/32] target-arm: move AArch32 SCR into security reglist Greg Bellows
2014-10-21 16:55 ` [Qemu-devel] [PATCH v7 15/32] target-arm: implement IRQ/FIQ routing to Monitor mode Greg Bellows
2014-10-21 16:55 ` [Qemu-devel] [PATCH v7 16/32] target-arm: respect SCR.FW, SCR.AW and SCTLR.NMFI Greg Bellows
2014-10-21 16:55 ` [Qemu-devel] [PATCH v7 17/32] target-arm: add NSACR register Greg Bellows
2014-10-21 16:55 ` [Qemu-devel] [PATCH v7 18/32] target-arm: add SDER definition Greg Bellows
2014-10-21 16:55 ` [Qemu-devel] [PATCH v7 19/32] target-arm: add MVBAR support Greg Bellows
2014-10-21 16:55 ` [Qemu-devel] [PATCH v7 20/32] target-arm: add SCTLR_EL3 and make SCTLR banked Greg Bellows
2014-10-21 16:55 ` [Qemu-devel] [PATCH v7 21/32] target-arm: make CSSELR banked Greg Bellows
2014-10-21 16:55 ` [Qemu-devel] [PATCH v7 22/32] target-arm: add TTBR0_EL3 and make TTBR0/1 banked Greg Bellows
2014-10-21 16:55 ` [Qemu-devel] [PATCH v7 23/32] target-arm: add TCR_EL3 and make TTBCR banked Greg Bellows
2014-10-21 16:55 ` [Qemu-devel] [PATCH v7 24/32] target-arm: make c2_mask and c2_base_mask banked Greg Bellows
2014-10-21 16:55 ` [Qemu-devel] [PATCH v7 25/32] target-arm: make DACR banked Greg Bellows
2014-10-21 16:55 ` [Qemu-devel] [PATCH v7 26/32] target-arm: make IFSR banked Greg Bellows
2014-10-21 16:55 ` [Qemu-devel] [PATCH v7 27/32] target-arm: make DFSR banked Greg Bellows
2014-10-21 16:55 ` [Qemu-devel] [PATCH v7 28/32] target-arm: make IFAR/DFAR banked Greg Bellows
2014-10-21 16:55 ` [Qemu-devel] [PATCH v7 29/32] target-arm: make PAR banked Greg Bellows
2014-10-21 16:55 ` [Qemu-devel] [PATCH v7 30/32] target-arm: make c13 cp regs banked (FCSEIDR, ...) Greg Bellows
2014-10-21 16:55 ` [Qemu-devel] [PATCH v7 31/32] target-arm: make MAIR0/1 banked Greg Bellows
2014-10-21 16:55 ` Greg Bellows [this message]
2014-10-23 14:19 ` [Qemu-devel] [PATCH v7 00/32] target-arm: add Security Extensions for CPUs Peter Maydell

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