From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:50400) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1XhdBc-0006ZX-Qw for qemu-devel@nongnu.org; Fri, 24 Oct 2014 07:37:41 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1XhdBb-0008R3-5r for qemu-devel@nongnu.org; Fri, 24 Oct 2014 07:37:40 -0400 Received: from mnementh.archaic.org.uk ([2001:8b0:1d0::1]:54280) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1XhdBb-0008OE-0N for qemu-devel@nongnu.org; Fri, 24 Oct 2014 07:37:39 -0400 Received: from pm215 by mnementh.archaic.org.uk with local (Exim 4.80) (envelope-from ) id 1XhdBS-0007wR-C6 for qemu-devel@nongnu.org; Fri, 24 Oct 2014 12:37:30 +0100 From: Peter Maydell Date: Fri, 24 Oct 2014 12:37:21 +0100 Message-Id: <1414150649-30428-16-git-send-email-peter.maydell@linaro.org> In-Reply-To: <1414150649-30428-1-git-send-email-peter.maydell@linaro.org> References: <1414150649-30428-1-git-send-email-peter.maydell@linaro.org> Subject: [Qemu-devel] [PULL 15/23] target-arm: Correct sense of the DCZID DZP bit List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org The DZP bit in the DCZID system register should be set if the control bits which prohibit use of the DC ZVA instruction have been set (it stands for Data Zero Prohibited). However we had the sense of the test inverted; fix this so that the bit reads correctly. To avoid this regressing the behaviour of the user-mode emulator, we must set the DZE bit in the SCTLR for that config so that userspace continues to see DZP as zero (it was getting the correct result by accident previously). Reported-by: Christopher Covington Signed-off-by: Peter Maydell Reviewed-by: Christopher Covington Message-id: 1412959792-20708-1-git-send-email-peter.maydell@linaro.org --- target-arm/cpu.c | 4 ++-- target-arm/helper.c | 2 +- 2 files changed, 3 insertions(+), 3 deletions(-) diff --git a/target-arm/cpu.c b/target-arm/cpu.c index e837f64..e0b82a6 100644 --- a/target-arm/cpu.c +++ b/target-arm/cpu.c @@ -108,8 +108,8 @@ static void arm_cpu_reset(CPUState *s) env->aarch64 = 1; #if defined(CONFIG_USER_ONLY) env->pstate = PSTATE_MODE_EL0t; - /* Userspace expects access to CTL_EL0 and the cache ops */ - env->cp15.c1_sys |= SCTLR_UCT | SCTLR_UCI; + /* Userspace expects access to DC ZVA, CTL_EL0 and the cache ops */ + env->cp15.c1_sys |= SCTLR_UCT | SCTLR_UCI | SCTLR_DZE; /* and to the FP/Neon instructions */ env->cp15.c1_coproc = deposit64(env->cp15.c1_coproc, 20, 2, 3); #else diff --git a/target-arm/helper.c b/target-arm/helper.c index d837820..53527c2 100644 --- a/target-arm/helper.c +++ b/target-arm/helper.c @@ -2018,7 +2018,7 @@ static uint64_t aa64_dczid_read(CPUARMState *env, const ARMCPRegInfo *ri) int dzp_bit = 1 << 4; /* DZP indicates whether DC ZVA access is allowed */ - if (aa64_zva_access(env, NULL) != CP_ACCESS_OK) { + if (aa64_zva_access(env, NULL) == CP_ACCESS_OK) { dzp_bit = 0; } return cpu->dcz_blocksize | dzp_bit; -- 1.9.1