From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:50377) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1XhdBb-0006ZF-VM for qemu-devel@nongnu.org; Fri, 24 Oct 2014 07:37:40 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1XhdBa-0008Qx-Ti for qemu-devel@nongnu.org; Fri, 24 Oct 2014 07:37:39 -0400 Received: from mnementh.archaic.org.uk ([2001:8b0:1d0::1]:54280) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1XhdBa-0008OE-OO for qemu-devel@nongnu.org; Fri, 24 Oct 2014 07:37:38 -0400 Received: from pm215 by mnementh.archaic.org.uk with local (Exim 4.80) (envelope-from ) id 1XhdBS-0007wW-E0 for qemu-devel@nongnu.org; Fri, 24 Oct 2014 12:37:30 +0100 From: Peter Maydell Date: Fri, 24 Oct 2014 12:37:22 +0100 Message-Id: <1414150649-30428-17-git-send-email-peter.maydell@linaro.org> In-Reply-To: <1414150649-30428-1-git-send-email-peter.maydell@linaro.org> References: <1414150649-30428-1-git-send-email-peter.maydell@linaro.org> Subject: [Qemu-devel] [PULL 16/23] target-arm: Report a valid L1Ip field in CTR_EL0 for CPU type "any" List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org For the CPU type "any" (only used with linux-user) we were reporting the L1Ip field as 0b00, which is reserved. Change this field to 0b10 instead, indicating a VIPT icache as the comment describes. Reported-by: Laurent Desnogues Signed-off-by: Peter Maydell Reviewed-by: Laurent Desnogues Message-id: 1412966807-20844-1-git-send-email-peter.maydell@linaro.org --- target-arm/cpu64.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/target-arm/cpu64.c b/target-arm/cpu64.c index a95367a..bb778b3d 100644 --- a/target-arm/cpu64.c +++ b/target-arm/cpu64.c @@ -151,7 +151,7 @@ static void aarch64_any_initfn(Object *obj) set_feature(&cpu->env, ARM_FEATURE_V8_SHA256); set_feature(&cpu->env, ARM_FEATURE_V8_PMULL); set_feature(&cpu->env, ARM_FEATURE_CRC); - cpu->ctr = 0x80030003; /* 32 byte I and D cacheline size, VIPT icache */ + cpu->ctr = 0x80038003; /* 32 byte I and D cacheline size, VIPT icache */ cpu->dcz_blocksize = 7; /* 512 bytes */ } #endif -- 1.9.1