From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:50374) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1XhdBb-0006ZA-Qh for qemu-devel@nongnu.org; Fri, 24 Oct 2014 07:37:45 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1XhdBa-0008QO-59 for qemu-devel@nongnu.org; Fri, 24 Oct 2014 07:37:39 -0400 Received: from mnementh.archaic.org.uk ([2001:8b0:1d0::1]:54280) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1XhdBZ-0008OE-U8 for qemu-devel@nongnu.org; Fri, 24 Oct 2014 07:37:38 -0400 Received: from pm215 by mnementh.archaic.org.uk with local (Exim 4.80) (envelope-from ) id 1XhdBS-0007wl-KO for qemu-devel@nongnu.org; Fri, 24 Oct 2014 12:37:30 +0100 From: Peter Maydell Date: Fri, 24 Oct 2014 12:37:25 +0100 Message-Id: <1414150649-30428-20-git-send-email-peter.maydell@linaro.org> In-Reply-To: <1414150649-30428-1-git-send-email-peter.maydell@linaro.org> References: <1414150649-30428-1-git-send-email-peter.maydell@linaro.org> Subject: [Qemu-devel] [PULL 19/23] target-arm: add arm_is_secure() function List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org From: Fabian Aggeler arm_is_secure() function allows to determine CPU security state if the CPU implements Security Extensions/EL3. arm_is_secure_below_el3() returns true if CPU is in secure state below EL3. Signed-off-by: Sergey Fedorov Signed-off-by: Fabian Aggeler Signed-off-by: Greg Bellows Reviewed-by: Peter Maydell Message-id: 1413910544-20150-3-git-send-email-greg.bellows@linaro.org Signed-off-by: Peter Maydell --- target-arm/cpu.h | 47 +++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 47 insertions(+) diff --git a/target-arm/cpu.h b/target-arm/cpu.h index e0e3f9b..44ed6fe 100644 --- a/target-arm/cpu.h +++ b/target-arm/cpu.h @@ -753,6 +753,53 @@ static inline int arm_feature(CPUARMState *env, int feature) return (env->features & (1ULL << feature)) != 0; } +#if !defined(CONFIG_USER_ONLY) +/* Return true if exception levels below EL3 are in secure state, + * or would be following an exception return to that level. + * Unlike arm_is_secure() (which is always a question about the + * _current_ state of the CPU) this doesn't care about the current + * EL or mode. + */ +static inline bool arm_is_secure_below_el3(CPUARMState *env) +{ + if (arm_feature(env, ARM_FEATURE_EL3)) { + return !(env->cp15.scr_el3 & SCR_NS); + } else { + /* If EL2 is not supported then the secure state is implementation + * defined, in which case QEMU defaults to non-secure. + */ + return false; + } +} + +/* Return true if the processor is in secure state */ +static inline bool arm_is_secure(CPUARMState *env) +{ + if (arm_feature(env, ARM_FEATURE_EL3)) { + if (is_a64(env) && extract32(env->pstate, 2, 2) == 3) { + /* CPU currently in AArch64 state and EL3 */ + return true; + } else if (!is_a64(env) && + (env->uncached_cpsr & CPSR_M) == ARM_CPU_MODE_MON) { + /* CPU currently in AArch32 state and monitor mode */ + return true; + } + } + return arm_is_secure_below_el3(env); +} + +#else +static inline bool arm_is_secure_below_el3(CPUARMState *env) +{ + return false; +} + +static inline bool arm_is_secure(CPUARMState *env) +{ + return false; +} +#endif + /* Return true if the specified exception level is running in AArch64 state. */ static inline bool arm_el_is_aa64(CPUARMState *env, int el) { -- 1.9.1