From: Peter Maydell <peter.maydell@linaro.org>
To: qemu-devel@nongnu.org
Subject: [Qemu-devel] [PULL 23/23] target-arm: A32: Emulate the SMC instruction
Date: Fri, 24 Oct 2014 12:37:29 +0100 [thread overview]
Message-ID: <1414150649-30428-24-git-send-email-peter.maydell@linaro.org> (raw)
In-Reply-To: <1414150649-30428-1-git-send-email-peter.maydell@linaro.org>
From: Fabian Aggeler <aggelerf@ethz.ch>
Implements SMC instruction in AArch32 using the A32 syndrome. When executing
SMC instruction from monitor CPU mode SCR.NS bit is reset.
Signed-off-by: Sergey Fedorov <s.fedorov@samsung.com>
Signed-off-by: Fabian Aggeler <aggelerf@ethz.ch>
Signed-off-by: Greg Bellows <greg.bellows@linaro.org>
Message-id: 1413910544-20150-7-git-send-email-greg.bellows@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
target-arm/helper.c | 11 +++++++++++
target-arm/op_helper.c | 3 +--
2 files changed, 12 insertions(+), 2 deletions(-)
diff --git a/target-arm/helper.c b/target-arm/helper.c
index c2b3539..c47487a 100644
--- a/target-arm/helper.c
+++ b/target-arm/helper.c
@@ -4091,6 +4091,12 @@ void arm_cpu_do_interrupt(CPUState *cs)
mask = CPSR_A | CPSR_I | CPSR_F;
offset = 4;
break;
+ case EXCP_SMC:
+ new_mode = ARM_CPU_MODE_MON;
+ addr = 0x08;
+ mask = CPSR_A | CPSR_I | CPSR_F;
+ offset = 0;
+ break;
default:
cpu_abort(cs, "Unhandled exception 0x%x\n", cs->exception_index);
return; /* Never happens. Keep compiler happy. */
@@ -4109,6 +4115,11 @@ void arm_cpu_do_interrupt(CPUState *cs)
*/
addr += env->cp15.vbar_el[1];
}
+
+ if ((env->uncached_cpsr & CPSR_M) == ARM_CPU_MODE_MON) {
+ env->cp15.scr_el3 &= ~SCR_NS;
+ }
+
switch_mode (env, new_mode);
/* For exceptions taken to AArch32 we must clear the SS bit in both
* PSTATE and in the old-state value we save to SPSR_<mode>, so zero it now.
diff --git a/target-arm/op_helper.c b/target-arm/op_helper.c
index 6cc3387..62012c3 100644
--- a/target-arm/op_helper.c
+++ b/target-arm/op_helper.c
@@ -429,8 +429,7 @@ void HELPER(pre_smc)(CPUARMState *env, uint32_t syndrome)
{
ARMCPU *cpu = arm_env_get_cpu(env);
int cur_el = arm_current_el(env);
- /* FIXME: Use real secure state. */
- bool secure = false;
+ bool secure = arm_is_secure(env);
bool smd = env->cp15.scr_el3 & SCR_SMD;
/* On ARMv8 AArch32, SMD only applies to NS state.
* On ARMv7 SMD only applies to NS state and only if EL2 is available.
--
1.9.1
next prev parent reply other threads:[~2014-10-24 11:37 UTC|newest]
Thread overview: 25+ messages / expand[flat|nested] mbox.gz Atom feed top
2014-10-24 11:37 [Qemu-devel] [PULL 00/23] target-arm queue Peter Maydell
2014-10-24 11:37 ` [Qemu-devel] [PULL 01/23] hmp: Remove "info pcmcia" Peter Maydell
2014-10-24 11:37 ` [Qemu-devel] [PULL 02/23] hw/arm/virt: mark timer in fdt as v8-compatible Peter Maydell
2014-10-24 11:37 ` [Qemu-devel] [PULL 03/23] hw/arm/boot: register cpu reset handlers if using -bios Peter Maydell
2014-10-24 11:37 ` [Qemu-devel] [PULL 04/23] disas/libvixl: Update to libvixl 1.6 Peter Maydell
2014-10-24 11:37 ` [Qemu-devel] [PULL 05/23] arm_gic: remove unused parameter Peter Maydell
2014-10-24 11:37 ` [Qemu-devel] [PULL 06/23] disas/libvixl/a64/instructions-a64.h: Remove unused constants Peter Maydell
2014-10-24 11:37 ` [Qemu-devel] [PULL 07/23] omap_gpmc.c: Remove duplicate assignment Peter Maydell
2014-10-24 11:37 ` [Qemu-devel] [PULL 08/23] target-arm: add powered off cpu state Peter Maydell
2014-10-24 11:37 ` [Qemu-devel] [PULL 09/23] target-arm: do not set do_interrupt handlers for ARM and AArch64 user modes Peter Maydell
2014-10-24 11:37 ` [Qemu-devel] [PULL 10/23] target-arm: add missing PSCI constants needed for PSCI emulation Peter Maydell
2014-10-24 11:37 ` [Qemu-devel] [PULL 11/23] target-arm: Handle SMC/HVC undef-if-no-ELx in pre_* helpers Peter Maydell
2014-10-24 11:37 ` [Qemu-devel] [PULL 12/23] target-arm: Add support for A32 and T32 HVC and SMC insns Peter Maydell
2014-10-24 11:37 ` [Qemu-devel] [PULL 13/23] target-arm: add emulation of PSCI calls for system emulation Peter Maydell
2014-10-24 11:37 ` [Qemu-devel] [PULL 14/23] arm/virt: enable PSCI emulation support " Peter Maydell
2014-10-24 11:37 ` [Qemu-devel] [PULL 15/23] target-arm: Correct sense of the DCZID DZP bit Peter Maydell
2014-10-24 11:37 ` [Qemu-devel] [PULL 16/23] target-arm: Report a valid L1Ip field in CTR_EL0 for CPU type "any" Peter Maydell
2014-10-24 11:37 ` [Qemu-devel] [PULL 17/23] target-arm: correctly UNDEF writes to FPINST/FPINST2 from EL0 Peter Maydell
2014-10-24 11:37 ` [Qemu-devel] [PULL 18/23] target-arm: increase arrays of registers R13 & R14 Peter Maydell
2014-10-24 11:37 ` [Qemu-devel] [PULL 19/23] target-arm: add arm_is_secure() function Peter Maydell
2014-10-24 11:37 ` [Qemu-devel] [PULL 20/23] target-arm: reject switching to monitor mode Peter Maydell
2014-10-24 11:37 ` [Qemu-devel] [PULL 21/23] target-arm: rename arm_current_pl to arm_current_el Peter Maydell
2014-10-24 11:37 ` [Qemu-devel] [PULL 22/23] target-arm: make arm_current_el() return EL3 Peter Maydell
2014-10-24 11:37 ` Peter Maydell [this message]
2014-10-24 12:56 ` [Qemu-devel] [PULL 00/23] target-arm queue Peter Maydell
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