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From: Peter Maydell <peter.maydell@linaro.org>
To: qemu-devel@nongnu.org
Subject: [Qemu-devel] [PULL 02/23] hw/arm/virt: mark timer in fdt as v8-compatible
Date: Fri, 24 Oct 2014 12:37:08 +0100	[thread overview]
Message-ID: <1414150649-30428-3-git-send-email-peter.maydell@linaro.org> (raw)
In-Reply-To: <1414150649-30428-1-git-send-email-peter.maydell@linaro.org>

From: Claudio Fontana <claudio.fontana@huawei.com>

check if the first cpu is an armv8 cpu, and if so, put
arm,armv8-timer in the compatible string list.

Note that due to this check, this patch moves the creation
of the timer fdt node to after the cpu creation loop.

Signed-off-by: Claudio Fontana <claudio.fontana@huawei.com>
Message-id: 1411736960-24206-1-git-send-email-hw.claudio@gmail.com
[PMM: updated to list arm,armv8-timer first]
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 hw/arm/virt.c | 15 ++++++++++++---
 1 file changed, 12 insertions(+), 3 deletions(-)

diff --git a/hw/arm/virt.c b/hw/arm/virt.c
index 8ea592e..5c010e5 100644
--- a/hw/arm/virt.c
+++ b/hw/arm/virt.c
@@ -240,14 +240,23 @@ static void fdt_add_timer_nodes(const VirtBoardInfo *vbi)
      * but for the GIC implementation provided by both QEMU and KVM
      * they are edge-triggered.
      */
+    ARMCPU *armcpu;
     uint32_t irqflags = GIC_FDT_IRQ_FLAGS_EDGE_LO_HI;
 
     irqflags = deposit32(irqflags, GIC_FDT_IRQ_PPI_CPU_START,
                          GIC_FDT_IRQ_PPI_CPU_WIDTH, (1 << vbi->smp_cpus) - 1);
 
     qemu_fdt_add_subnode(vbi->fdt, "/timer");
-    qemu_fdt_setprop_string(vbi->fdt, "/timer",
-                                "compatible", "arm,armv7-timer");
+
+    armcpu = ARM_CPU(qemu_get_cpu(0));
+    if (arm_feature(&armcpu->env, ARM_FEATURE_V8)) {
+        const char compat[] = "arm,armv8-timer\0arm,armv7-timer";
+        qemu_fdt_setprop(vbi->fdt, "/timer", "compatible",
+                         compat, sizeof(compat));
+    } else {
+        qemu_fdt_setprop_string(vbi->fdt, "/timer", "compatible",
+                                "arm,armv7-timer");
+    }
     qemu_fdt_setprop_cells(vbi->fdt, "/timer", "interrupts",
                                GIC_FDT_IRQ_TYPE_PPI, 13, irqflags,
                                GIC_FDT_IRQ_TYPE_PPI, 14, irqflags,
@@ -555,7 +564,6 @@ static void machvirt_init(MachineState *machine)
     }
 
     create_fdt(vbi);
-    fdt_add_timer_nodes(vbi);
 
     for (n = 0; n < smp_cpus; n++) {
         ObjectClass *oc = cpu_class_by_name(TYPE_ARM_CPU, cpu_model);
@@ -579,6 +587,7 @@ static void machvirt_init(MachineState *machine)
 
         object_property_set_bool(cpuobj, true, "realized", NULL);
     }
+    fdt_add_timer_nodes(vbi);
     fdt_add_cpu_nodes(vbi);
     fdt_add_psci_node(vbi);
 
-- 
1.9.1

  parent reply	other threads:[~2014-10-24 11:37 UTC|newest]

Thread overview: 25+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2014-10-24 11:37 [Qemu-devel] [PULL 00/23] target-arm queue Peter Maydell
2014-10-24 11:37 ` [Qemu-devel] [PULL 01/23] hmp: Remove "info pcmcia" Peter Maydell
2014-10-24 11:37 ` Peter Maydell [this message]
2014-10-24 11:37 ` [Qemu-devel] [PULL 03/23] hw/arm/boot: register cpu reset handlers if using -bios Peter Maydell
2014-10-24 11:37 ` [Qemu-devel] [PULL 04/23] disas/libvixl: Update to libvixl 1.6 Peter Maydell
2014-10-24 11:37 ` [Qemu-devel] [PULL 05/23] arm_gic: remove unused parameter Peter Maydell
2014-10-24 11:37 ` [Qemu-devel] [PULL 06/23] disas/libvixl/a64/instructions-a64.h: Remove unused constants Peter Maydell
2014-10-24 11:37 ` [Qemu-devel] [PULL 07/23] omap_gpmc.c: Remove duplicate assignment Peter Maydell
2014-10-24 11:37 ` [Qemu-devel] [PULL 08/23] target-arm: add powered off cpu state Peter Maydell
2014-10-24 11:37 ` [Qemu-devel] [PULL 09/23] target-arm: do not set do_interrupt handlers for ARM and AArch64 user modes Peter Maydell
2014-10-24 11:37 ` [Qemu-devel] [PULL 10/23] target-arm: add missing PSCI constants needed for PSCI emulation Peter Maydell
2014-10-24 11:37 ` [Qemu-devel] [PULL 11/23] target-arm: Handle SMC/HVC undef-if-no-ELx in pre_* helpers Peter Maydell
2014-10-24 11:37 ` [Qemu-devel] [PULL 12/23] target-arm: Add support for A32 and T32 HVC and SMC insns Peter Maydell
2014-10-24 11:37 ` [Qemu-devel] [PULL 13/23] target-arm: add emulation of PSCI calls for system emulation Peter Maydell
2014-10-24 11:37 ` [Qemu-devel] [PULL 14/23] arm/virt: enable PSCI emulation support " Peter Maydell
2014-10-24 11:37 ` [Qemu-devel] [PULL 15/23] target-arm: Correct sense of the DCZID DZP bit Peter Maydell
2014-10-24 11:37 ` [Qemu-devel] [PULL 16/23] target-arm: Report a valid L1Ip field in CTR_EL0 for CPU type "any" Peter Maydell
2014-10-24 11:37 ` [Qemu-devel] [PULL 17/23] target-arm: correctly UNDEF writes to FPINST/FPINST2 from EL0 Peter Maydell
2014-10-24 11:37 ` [Qemu-devel] [PULL 18/23] target-arm: increase arrays of registers R13 & R14 Peter Maydell
2014-10-24 11:37 ` [Qemu-devel] [PULL 19/23] target-arm: add arm_is_secure() function Peter Maydell
2014-10-24 11:37 ` [Qemu-devel] [PULL 20/23] target-arm: reject switching to monitor mode Peter Maydell
2014-10-24 11:37 ` [Qemu-devel] [PULL 21/23] target-arm: rename arm_current_pl to arm_current_el Peter Maydell
2014-10-24 11:37 ` [Qemu-devel] [PULL 22/23] target-arm: make arm_current_el() return EL3 Peter Maydell
2014-10-24 11:37 ` [Qemu-devel] [PULL 23/23] target-arm: A32: Emulate the SMC instruction Peter Maydell
2014-10-24 12:56 ` [Qemu-devel] [PULL 00/23] target-arm queue Peter Maydell

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