From: Peter Maydell <peter.maydell@linaro.org>
To: qemu-devel@nongnu.org
Subject: [Qemu-devel] [PULL 05/23] arm_gic: remove unused parameter.
Date: Fri, 24 Oct 2014 12:37:11 +0100 [thread overview]
Message-ID: <1414150649-30428-6-git-send-email-peter.maydell@linaro.org> (raw)
In-Reply-To: <1414150649-30428-1-git-send-email-peter.maydell@linaro.org>
From: KONRAD Frederic <fred.konrad@greensocs.com>
This removes num_irq parameter from gic_init_irqs_and_distributor as it is not
used.
Signed-off-by: KONRAD Frederic <fred.konrad@greensocs.com>
Message-id: 1412859651-15060-1-git-send-email-fred.konrad@greensocs.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
hw/intc/arm_gic.c | 4 ++--
hw/intc/armv7m_nvic.c | 2 +-
hw/intc/gic_internal.h | 2 +-
3 files changed, 4 insertions(+), 4 deletions(-)
diff --git a/hw/intc/arm_gic.c b/hw/intc/arm_gic.c
index db9110c..270ce05 100644
--- a/hw/intc/arm_gic.c
+++ b/hw/intc/arm_gic.c
@@ -769,7 +769,7 @@ static const MemoryRegionOps gic_cpu_ops = {
.endianness = DEVICE_NATIVE_ENDIAN,
};
-void gic_init_irqs_and_distributor(GICState *s, int num_irq)
+void gic_init_irqs_and_distributor(GICState *s)
{
SysBusDevice *sbd = SYS_BUS_DEVICE(s);
int i;
@@ -808,7 +808,7 @@ static void arm_gic_realize(DeviceState *dev, Error **errp)
return;
}
- gic_init_irqs_and_distributor(s, s->num_irq);
+ gic_init_irqs_and_distributor(s);
/* Memory regions for the CPU interfaces (NVIC doesn't have these):
* a region for "CPU interface for this core", then a region for
diff --git a/hw/intc/armv7m_nvic.c b/hw/intc/armv7m_nvic.c
index 1a7af45..d0543d4 100644
--- a/hw/intc/armv7m_nvic.c
+++ b/hw/intc/armv7m_nvic.c
@@ -488,7 +488,7 @@ static void armv7m_nvic_realize(DeviceState *dev, Error **errp)
error_propagate(errp, local_err);
return;
}
- gic_init_irqs_and_distributor(&s->gic, s->num_irq);
+ gic_init_irqs_and_distributor(&s->gic);
/* The NVIC and system controller register area looks like this:
* 0..0xff : system control registers, including systick
* 0x100..0xcff : GIC-like registers
diff --git a/hw/intc/gic_internal.h b/hw/intc/gic_internal.h
index 48a58d7..e87ef36 100644
--- a/hw/intc/gic_internal.h
+++ b/hw/intc/gic_internal.h
@@ -59,7 +59,7 @@ void gic_set_pending_private(GICState *s, int cpu, int irq);
uint32_t gic_acknowledge_irq(GICState *s, int cpu);
void gic_complete_irq(GICState *s, int cpu, int irq);
void gic_update(GICState *s);
-void gic_init_irqs_and_distributor(GICState *s, int num_irq);
+void gic_init_irqs_and_distributor(GICState *s);
void gic_set_priority(GICState *s, int cpu, int irq, uint8_t val);
static inline bool gic_test_pending(GICState *s, int irq, int cm)
--
1.9.1
next prev parent reply other threads:[~2014-10-24 11:37 UTC|newest]
Thread overview: 25+ messages / expand[flat|nested] mbox.gz Atom feed top
2014-10-24 11:37 [Qemu-devel] [PULL 00/23] target-arm queue Peter Maydell
2014-10-24 11:37 ` [Qemu-devel] [PULL 01/23] hmp: Remove "info pcmcia" Peter Maydell
2014-10-24 11:37 ` [Qemu-devel] [PULL 02/23] hw/arm/virt: mark timer in fdt as v8-compatible Peter Maydell
2014-10-24 11:37 ` [Qemu-devel] [PULL 03/23] hw/arm/boot: register cpu reset handlers if using -bios Peter Maydell
2014-10-24 11:37 ` [Qemu-devel] [PULL 04/23] disas/libvixl: Update to libvixl 1.6 Peter Maydell
2014-10-24 11:37 ` Peter Maydell [this message]
2014-10-24 11:37 ` [Qemu-devel] [PULL 06/23] disas/libvixl/a64/instructions-a64.h: Remove unused constants Peter Maydell
2014-10-24 11:37 ` [Qemu-devel] [PULL 07/23] omap_gpmc.c: Remove duplicate assignment Peter Maydell
2014-10-24 11:37 ` [Qemu-devel] [PULL 08/23] target-arm: add powered off cpu state Peter Maydell
2014-10-24 11:37 ` [Qemu-devel] [PULL 09/23] target-arm: do not set do_interrupt handlers for ARM and AArch64 user modes Peter Maydell
2014-10-24 11:37 ` [Qemu-devel] [PULL 10/23] target-arm: add missing PSCI constants needed for PSCI emulation Peter Maydell
2014-10-24 11:37 ` [Qemu-devel] [PULL 11/23] target-arm: Handle SMC/HVC undef-if-no-ELx in pre_* helpers Peter Maydell
2014-10-24 11:37 ` [Qemu-devel] [PULL 12/23] target-arm: Add support for A32 and T32 HVC and SMC insns Peter Maydell
2014-10-24 11:37 ` [Qemu-devel] [PULL 13/23] target-arm: add emulation of PSCI calls for system emulation Peter Maydell
2014-10-24 11:37 ` [Qemu-devel] [PULL 14/23] arm/virt: enable PSCI emulation support " Peter Maydell
2014-10-24 11:37 ` [Qemu-devel] [PULL 15/23] target-arm: Correct sense of the DCZID DZP bit Peter Maydell
2014-10-24 11:37 ` [Qemu-devel] [PULL 16/23] target-arm: Report a valid L1Ip field in CTR_EL0 for CPU type "any" Peter Maydell
2014-10-24 11:37 ` [Qemu-devel] [PULL 17/23] target-arm: correctly UNDEF writes to FPINST/FPINST2 from EL0 Peter Maydell
2014-10-24 11:37 ` [Qemu-devel] [PULL 18/23] target-arm: increase arrays of registers R13 & R14 Peter Maydell
2014-10-24 11:37 ` [Qemu-devel] [PULL 19/23] target-arm: add arm_is_secure() function Peter Maydell
2014-10-24 11:37 ` [Qemu-devel] [PULL 20/23] target-arm: reject switching to monitor mode Peter Maydell
2014-10-24 11:37 ` [Qemu-devel] [PULL 21/23] target-arm: rename arm_current_pl to arm_current_el Peter Maydell
2014-10-24 11:37 ` [Qemu-devel] [PULL 22/23] target-arm: make arm_current_el() return EL3 Peter Maydell
2014-10-24 11:37 ` [Qemu-devel] [PULL 23/23] target-arm: A32: Emulate the SMC instruction Peter Maydell
2014-10-24 12:56 ` [Qemu-devel] [PULL 00/23] target-arm queue Peter Maydell
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