From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:37926) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1XjCNK-0005ul-Au for qemu-devel@nongnu.org; Tue, 28 Oct 2014 15:24:15 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1XjCNI-00069J-Tf for qemu-devel@nongnu.org; Tue, 28 Oct 2014 15:24:14 -0400 Received: from mnementh.archaic.org.uk ([2001:8b0:1d0::1]:54313) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1XjCNI-00067q-NK for qemu-devel@nongnu.org; Tue, 28 Oct 2014 15:24:12 -0400 From: Peter Maydell Date: Tue, 28 Oct 2014 19:24:04 +0000 Message-Id: <1414524244-20316-6-git-send-email-peter.maydell@linaro.org> In-Reply-To: <1414524244-20316-1-git-send-email-peter.maydell@linaro.org> References: <1414524244-20316-1-git-send-email-peter.maydell@linaro.org> Subject: [Qemu-devel] [PATCH 5/5] target-arm/translate.c: Don't pass CPUARMState * to disas_arm_insn() List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org Cc: patches@linaro.org Refactor to avoid passing a CPUARMState * to disas_arm_insn(). To do this we move the "read insn from memory" code to the callsite and pass the insn to the function instead. Signed-off-by: Peter Maydell --- target-arm/translate.c | 11 +++++------ 1 file changed, 5 insertions(+), 6 deletions(-) diff --git a/target-arm/translate.c b/target-arm/translate.c index 9e2dda2..932fa03 100644 --- a/target-arm/translate.c +++ b/target-arm/translate.c @@ -7560,18 +7560,15 @@ static void gen_srs(DisasContext *s, tcg_temp_free_i32(addr); } -static void disas_arm_insn(CPUARMState * env, DisasContext *s) +static void disas_arm_insn(DisasContext *s, unsigned int insn) { - unsigned int cond, insn, val, op1, i, shift, rm, rs, rn, rd, sh; + unsigned int cond, val, op1, i, shift, rm, rs, rn, rd, sh; TCGv_i32 tmp; TCGv_i32 tmp2; TCGv_i32 tmp3; TCGv_i32 addr; TCGv_i64 tmp64; - insn = arm_ldl_code(env, s->pc, s->bswap_code); - s->pc += 4; - /* M variants do not implement ARM mode. */ if (arm_dc_feature(s, ARM_FEATURE_M)) { goto illegal_op; @@ -11199,7 +11196,9 @@ static inline void gen_intermediate_code_internal(ARMCPU *cpu, } } } else { - disas_arm_insn(env, dc); + unsigned int insn = arm_ldl_code(env, dc->pc, dc->bswap_code); + dc->pc += 4; + disas_arm_insn(dc, insn); } if (dc->condjmp && !dc->is_jmp) { -- 1.9.1