From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:38467) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1XjIHk-0004d2-NI for qemu-devel@nongnu.org; Tue, 28 Oct 2014 21:42:57 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1XjIHf-0000z4-CK for qemu-devel@nongnu.org; Tue, 28 Oct 2014 21:42:52 -0400 Received: from mailapp01.imgtec.com ([195.59.15.196]:10255) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1XjIHf-0000ys-6g for qemu-devel@nongnu.org; Tue, 28 Oct 2014 21:42:47 -0400 From: Yongbok Kim Date: Wed, 29 Oct 2014 01:42:08 +0000 Message-ID: <1414546928-54642-21-git-send-email-yongbok.kim@imgtec.com> In-Reply-To: <1414546928-54642-1-git-send-email-yongbok.kim@imgtec.com> References: <1414546928-54642-1-git-send-email-yongbok.kim@imgtec.com> MIME-Version: 1.0 Content-Type: text/plain Subject: [Qemu-devel] [PATCH v2 20/20] target-mips: add MSA support to mips32r5-generic List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org Cc: leon.alrae@imgtec.com, aurelien@aurel32.net add MSA support to mips32r5-generic core definition Signed-off-by: Yongbok Kim --- target-mips/translate_init.c | 4 ++-- 1 files changed, 2 insertions(+), 2 deletions(-) diff --git a/target-mips/translate_init.c b/target-mips/translate_init.c index 8fb8bf8..0b4b597 100644 --- a/target-mips/translate_init.c +++ b/target-mips/translate_init.c @@ -358,7 +358,7 @@ static const mips_def_t mips_defs[] = (0 << CP0C1_DS) | (3 << CP0C1_DL) | (1 << CP0C1_DA) | (1 << CP0C1_CA), .CP0_Config2 = MIPS_CONFIG2, - .CP0_Config3 = MIPS_CONFIG3 | (1U << CP0C3_M), + .CP0_Config3 = MIPS_CONFIG3 | (1U << CP0C3_M) | (1 << CP0C3_MSAP), .CP0_Config4 = MIPS_CONFIG4 | (1U << CP0C4_M), .CP0_Config4_rw_bitmask = 0, .CP0_Config5 = MIPS_CONFIG5 | (1 << CP0C5_UFR), @@ -376,7 +376,7 @@ static const mips_def_t mips_defs[] = (0x93 << FCR0_PRID), .SEGBITS = 32, .PABITS = 32, - .insn_flags = CPU_MIPS32R5 | ASE_MIPS16 | ASE_DSP | ASE_DSPR2, + .insn_flags = CPU_MIPS32R5 | ASE_MIPS16 | ASE_DSP | ASE_DSPR2 | ASE_MSA, .mmu_type = MMU_TYPE_R4000, }, #if defined(TARGET_MIPS64) -- 1.7.4