From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:45999) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1XjO4z-0000Ph-6T for qemu-devel@nongnu.org; Wed, 29 Oct 2014 03:54:12 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1XjO4q-0008W7-EJ for qemu-devel@nongnu.org; Wed, 29 Oct 2014 03:54:05 -0400 Received: from cantor2.suse.de ([195.135.220.15]:56470 helo=mx2.suse.de) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1XjO4q-0008VF-3S for qemu-devel@nongnu.org; Wed, 29 Oct 2014 03:53:56 -0400 From: Hannes Reinecke Date: Wed, 29 Oct 2014 08:53:46 +0100 Message-Id: <1414569232-21357-12-git-send-email-hare@suse.de> In-Reply-To: <1414569232-21357-1-git-send-email-hare@suse.de> References: <1414569232-21357-1-git-send-email-hare@suse.de> Subject: [Qemu-devel] [PATCH 11/17] megasas: Decode register names List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org Cc: Hannes Reinecke , Paolo Bonzini , Nic Bellinger , Andreas Faerber , Alexander Graf To ease debugging we should be decoding the register names. Signed-off-by: Hannes Reinecke --- hw/scsi/megasas.c | 23 ++++++++++++++++++++--- trace-events | 4 ++-- 2 files changed, 22 insertions(+), 5 deletions(-) diff --git a/hw/scsi/megasas.c b/hw/scsi/megasas.c index f5c4318..56336b0 100644 --- a/hw/scsi/megasas.c +++ b/hw/scsi/megasas.c @@ -1991,6 +1991,7 @@ static uint64_t megasas_mmio_read(void *opaque, hwaddr addr, switch (addr) { case MFI_IDB: retval = 0; + trace_megasas_mmio_readl("MFI_IDB", retval); break; case MFI_OMSG0: case MFI_OSP0: @@ -1998,29 +1999,35 @@ static uint64_t megasas_mmio_read(void *opaque, hwaddr addr, (s->fw_state & MFI_FWSTATE_MASK) | ((s->fw_sge & 0xff) << 16) | (s->fw_cmds & 0xFFFF); + trace_megasas_mmio_readl(addr == MFI_OMSG0 ? "MFI_OMSG0" : "MFI_OSP0", + retval); break; case MFI_OSTS: if (megasas_intr_enabled(s) && s->doorbell) { retval = base_class->osts; } + trace_megasas_mmio_readl("MFI_OSTS", retval); break; case MFI_OMSK: retval = s->intr_mask; + trace_megasas_mmio_readl("MFI_OMSK", retval); break; case MFI_ODCR0: retval = s->doorbell; + trace_megasas_mmio_readl("MFI_ODCR0", retval); break; case MFI_DIAG: retval = s->diag; + trace_megasas_mmio_readl("MFI_DIAG", retval); break; case MFI_OSP1: retval = 15; + trace_megasas_mmio_readl("MFI_OSP1", retval); break; default: trace_megasas_mmio_invalid_readl(addr); break; } - trace_megasas_mmio_readl(addr, retval); return retval; } @@ -2035,9 +2042,9 @@ static void megasas_mmio_write(void *opaque, hwaddr addr, uint32_t frame_count; int i; - trace_megasas_mmio_writel(addr, val); switch (addr) { case MFI_IDB: + trace_megasas_mmio_writel("MFI_IDB", val); if (val & MFI_FWINIT_ABORT) { /* Abort all pending cmds */ for (i = 0; i < s->fw_cmds; i++) { @@ -2057,6 +2064,7 @@ static void megasas_mmio_write(void *opaque, hwaddr addr, } break; case MFI_OMSK: + trace_megasas_mmio_writel("MFI_OMSK", val); s->intr_mask = val; if (!megasas_intr_enabled(s) && !msi_enabled(pci_dev) && @@ -2078,6 +2086,7 @@ static void megasas_mmio_write(void *opaque, hwaddr addr, } break; case MFI_ODCR0: + trace_megasas_mmio_writel("MFI_ODCR0", val); s->doorbell = 0; if (s->producer_pa && megasas_intr_enabled(s)) { /* Update reply queue pointer */ @@ -2091,14 +2100,20 @@ static void megasas_mmio_write(void *opaque, hwaddr addr, } break; case MFI_IQPH: + trace_megasas_mmio_writel("MFI_IQPH", val); /* Received high 32 bits of a 64 bit MFI frame address */ s->frame_hi = val; break; case MFI_IQPL: + trace_megasas_mmio_writel("MFI_IQPL", val); /* Received low 32 bits of a 64 bit MFI frame address */ /* Fallthrough */ case MFI_IQP: - /* Received 64 bit MFI frame address */ + if (addr == MFI_IQP) { + trace_megasas_mmio_writel("MFI_IQP", val); + /* Received 64 bit MFI frame address */ + s->frame_hi = 0; + } frame_addr = (val & ~0x1F); /* Add possible 64 bit offset */ frame_addr |= ((uint64_t)s->frame_hi << 32); @@ -2107,6 +2122,7 @@ static void megasas_mmio_write(void *opaque, hwaddr addr, megasas_handle_frame(s, frame_addr, frame_count); break; case MFI_SEQ: + trace_megasas_mmio_writel("MFI_SEQ", val); /* Magic sequence to start ADP reset */ if (adp_reset_seq[s->adp_reset] == val) { s->adp_reset++; @@ -2119,6 +2135,7 @@ static void megasas_mmio_write(void *opaque, hwaddr addr, } break; case MFI_DIAG: + trace_megasas_mmio_writel("MFI_DIAG", val); /* ADP reset */ if ((s->diag & MFI_DIAG_WRITE_ENABLE) && (val & MFI_DIAG_RESET_ADP)) { diff --git a/trace-events b/trace-events index 380aa83..69b95f5 100644 --- a/trace-events +++ b/trace-events @@ -764,9 +764,9 @@ megasas_intr_enabled(void) "Interrupts enabled" megasas_intr_disabled(void) "Interrupts disabled" megasas_msix_enabled(int vector) "vector %d" megasas_msi_enabled(int vector) "vector %d" -megasas_mmio_readl(unsigned long addr, uint32_t val) "addr 0x%lx: 0x%x" +megasas_mmio_readl(const char *reg, uint32_t val) "reg %s: 0x%x" megasas_mmio_invalid_readl(unsigned long addr) "addr 0x%lx" -megasas_mmio_writel(uint32_t addr, uint32_t val) "addr 0x%x: 0x%x" +megasas_mmio_writel(const char *reg, uint32_t val) "reg %s: 0x%x" megasas_mmio_invalid_writel(uint32_t addr, uint32_t val) "addr 0x%x: 0x%x" # hw/audio/milkymist-ac97.c -- 1.8.4.5