From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:44114) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1XjSGf-0005u5-0s for qemu-devel@nongnu.org; Wed, 29 Oct 2014 08:22:30 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1XjSGY-0006TL-Av for qemu-devel@nongnu.org; Wed, 29 Oct 2014 08:22:24 -0400 Received: from mail.uni-paderborn.de ([131.234.142.9]:52708) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1XjSGY-0006SG-1J for qemu-devel@nongnu.org; Wed, 29 Oct 2014 08:22:18 -0400 From: Bastian Koppelmann Date: Wed, 29 Oct 2014 13:22:18 +0000 Message-Id: <1414588941-845-3-git-send-email-kbastian@mail.uni-paderborn.de> In-Reply-To: <1414588941-845-1-git-send-email-kbastian@mail.uni-paderborn.de> References: <1414588941-845-1-git-send-email-kbastian@mail.uni-paderborn.de> Subject: [Qemu-devel] [PATCH 2/5] target-tricore: Add instructions of BRC opcode format List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org Cc: peter.maydell@linaro.org, rth@twiddle.net Add instructions of BRC opcode format. Fixed OP2_BRC_JGE -> OP2_32_BRC_JGE. Signed-off-by: Bastian Koppelmann --- target-tricore/translate.c | 53 +++++++++++++++++++++++++++++++++++++++- target-tricore/tricore-opcodes.h | 6 +++-- 2 files changed, 56 insertions(+), 3 deletions(-) diff --git a/target-tricore/translate.c b/target-tricore/translate.c index 28e268e..789f005 100644 --- a/target-tricore/translate.c +++ b/target-tricore/translate.c @@ -665,6 +665,47 @@ static void gen_compute_branch(DisasContext *ctx, uint32_t opc, int r1, tcg_gen_movi_tl(cpu_gpr_a[11], ctx->next_pc); gen_goto_tb(ctx, 0, ctx->pc + offset * 2); break; +/* BOL format */ + case OPCM_32_BRC_EQ_NEQ: + if (MASK_OP_BRC_OP2(ctx->opcode) == OPC2_32_BRC_JEQ) { + gen_branch_condi(ctx, TCG_COND_EQ, cpu_gpr_d[r1], constant, offset); + } else { + gen_branch_condi(ctx, TCG_COND_NE, cpu_gpr_d[r1], constant, offset); + } + break; + case OPCM_32_BRC_GE: + if (MASK_OP_BRC_OP2(ctx->opcode) == OP2_32_BRC_JGE) { + gen_branch_condi(ctx, TCG_COND_GE, cpu_gpr_d[r1], constant, offset); + } else { + constant = MASK_OP_BRC_CONST4(ctx->opcode); + gen_branch_condi(ctx, TCG_COND_GEU, cpu_gpr_d[r1], constant, + offset); + } + break; + case OPCM_32_BRC_JLT: + if (MASK_OP_BRC_OP2(ctx->opcode) == OPC2_32_BRC_JLT) { + gen_branch_condi(ctx, TCG_COND_LT, cpu_gpr_d[r1], constant, offset); + } else { + constant = MASK_OP_BRC_CONST4(ctx->opcode); + gen_branch_condi(ctx, TCG_COND_LTU, cpu_gpr_d[r1], constant, + offset); + } + break; + case OPCM_32_BRC_JNE: + temp = tcg_temp_new(); + if (MASK_OP_BRC_OP2(ctx->opcode) == OPC2_32_BRC_JNED) { + tcg_gen_mov_tl(temp, cpu_gpr_d[r1]); + /* subi is unconditional */ + tcg_gen_subi_tl(cpu_gpr_d[r1], cpu_gpr_d[r1], 1); + gen_branch_condi(ctx, TCG_COND_NE, temp, constant, offset); + } else { + tcg_gen_mov_tl(temp, cpu_gpr_d[r1]); + /* addi is unconditional */ + tcg_gen_addi_tl(cpu_gpr_d[r1], cpu_gpr_d[r1], 1); + gen_branch_condi(ctx, TCG_COND_NE, temp, constant, offset); + } + tcg_temp_free(temp); + break; default: printf("Branch Error at %x\n", ctx->pc); } @@ -2324,7 +2365,7 @@ static void decode_32Bit_opc(CPUTriCoreState *env, DisasContext *ctx) int op1; int32_t r1; int32_t address; - int8_t b; + int8_t b, const4; int32_t bpos; TCGv temp, temp2; @@ -2453,6 +2494,16 @@ static void decode_32Bit_opc(CPUTriCoreState *env, DisasContext *ctx) case OPC1_32_BOL_ST_A_LONGOFF: decode_bol_opc(env, ctx, op1); break; +/* BRC Format */ + case OPCM_32_BRC_EQ_NEQ: + case OPCM_32_BRC_GE: + case OPCM_32_BRC_JLT: + case OPCM_32_BRC_JNE: + const4 = MASK_OP_BRC_CONST4_SEXT(ctx->opcode); + address = MASK_OP_BRC_DISP15_SEXT(ctx->opcode); + r1 = MASK_OP_BRC_S1(ctx->opcode); + gen_compute_branch(ctx, op1, r1, 0, const4, address); + break; } } diff --git a/target-tricore/tricore-opcodes.h b/target-tricore/tricore-opcodes.h index ba07d85..2d18624 100644 --- a/target-tricore/tricore-opcodes.h +++ b/target-tricore/tricore-opcodes.h @@ -124,7 +124,9 @@ /* BRC Format */ #define MASK_OP_BRC_OP2(op) MASK_BITS_SHIFT(op, 31, 31) #define MASK_OP_BRC_DISP15(op) MASK_BITS_SHIFT(op, 16, 30) +#define MASK_OP_BRC_DISP15_SEXT(op) MASK_BITS_SHIFT_SEXT(op, 16, 30) #define MASK_OP_BRC_CONST4(op) MASK_BITS_SHIFT(op, 12, 15) +#define MASK_OP_BRC_CONST4_SEXT(op) MASK_BITS_SHIFT_SEXT(op, 12, 15) #define MASK_OP_BRC_S1(op) MASK_BITS_SHIFT(op, 8, 11) /* BRN Format */ @@ -765,8 +767,8 @@ enum { }; /* OPCM_32_BRC_GE */ enum { - OP2_BRC_JGE = 0x00, - OPC_BRC_JGE_U = 0x01, + OP2_32_BRC_JGE = 0x00, + OPC_32_BRC_JGE_U = 0x01, }; /* OPCM_32_BRC_JLT */ enum { -- 2.1.2