From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:44123) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1XjSGi-0005u8-C3 for qemu-devel@nongnu.org; Wed, 29 Oct 2014 08:22:33 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1XjSGY-0006TX-Lc for qemu-devel@nongnu.org; Wed, 29 Oct 2014 08:22:28 -0400 Received: from mail.uni-paderborn.de ([131.234.142.9]:52721) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1XjSGY-0006Sw-G6 for qemu-devel@nongnu.org; Wed, 29 Oct 2014 08:22:18 -0400 From: Bastian Koppelmann Date: Wed, 29 Oct 2014 13:22:19 +0000 Message-Id: <1414588941-845-4-git-send-email-kbastian@mail.uni-paderborn.de> In-Reply-To: <1414588941-845-1-git-send-email-kbastian@mail.uni-paderborn.de> References: <1414588941-845-1-git-send-email-kbastian@mail.uni-paderborn.de> Subject: [Qemu-devel] [PATCH 3/5] target-tricore: Add instructions of BRN opcode format List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org Cc: peter.maydell@linaro.org, rth@twiddle.net Add instructions of BRN opcode format. Add MASK_OP_BRN_DISP15_SEXT. Signed-off-by: Bastian Koppelmann --- target-tricore/translate.c | 30 ++++++++++++++++++++++++++++++ target-tricore/tricore-opcodes.h | 1 + 2 files changed, 31 insertions(+) diff --git a/target-tricore/translate.c b/target-tricore/translate.c index 789f005..0c69f1f 100644 --- a/target-tricore/translate.c +++ b/target-tricore/translate.c @@ -568,6 +568,7 @@ static void gen_compute_branch(DisasContext *ctx, uint32_t opc, int r1, int r2 , int32_t constant , int32_t offset) { TCGv temp; + int l1, n; switch (opc) { /* SB-format jumps */ @@ -706,6 +707,24 @@ static void gen_compute_branch(DisasContext *ctx, uint32_t opc, int r1, } tcg_temp_free(temp); break; +/* BRN format */ + case OPCM_32_BRN_JTT: + l1 = gen_new_label(); + n = MASK_OP_BRN_N(ctx->opcode); + + temp = tcg_temp_new(); + tcg_gen_andi_tl(temp, cpu_gpr_d[r1], (1 << n)); + + if (MASK_OP_BRN_OP2(ctx->opcode) == OPC2_32_BRN_JNZ_T) { + tcg_gen_brcondi_tl(TCG_COND_NE, temp, 0, l1); + } else { + tcg_gen_brcondi_tl(TCG_COND_EQ, temp, 0, l1); + } + gen_goto_tb(ctx, 0, ctx->next_pc); + gen_set_label(l1); + gen_goto_tb(ctx, 1, ctx->pc + offset * 2); + tcg_temp_free(temp); + break; default: printf("Branch Error at %x\n", ctx->pc); } @@ -2371,6 +2390,11 @@ static void decode_32Bit_opc(CPUTriCoreState *env, DisasContext *ctx) op1 = MASK_OP_MAJOR(ctx->opcode); + /* handle JNZ.T opcode only being 6 bit long */ + if (unlikely((op1 & 0x3f) == OPCM_32_BRN_JTT)) { + op1 = OPCM_32_BRN_JTT; + } + switch (op1) { /* ABS-format */ case OPCM_32_ABS_LDW: @@ -2504,6 +2528,12 @@ static void decode_32Bit_opc(CPUTriCoreState *env, DisasContext *ctx) r1 = MASK_OP_BRC_S1(ctx->opcode); gen_compute_branch(ctx, op1, r1, 0, const4, address); break; +/* BRN Format */ + case OPCM_32_BRN_JTT: + address = MASK_OP_BRN_DISP15_SEXT(ctx->opcode); + r1 = MASK_OP_BRN_S1(ctx->opcode); + gen_compute_branch(ctx, op1, r1, 0, 0, address); + break; } } diff --git a/target-tricore/tricore-opcodes.h b/target-tricore/tricore-opcodes.h index 2d18624..3622d38 100644 --- a/target-tricore/tricore-opcodes.h +++ b/target-tricore/tricore-opcodes.h @@ -132,6 +132,7 @@ /* BRN Format */ #define MASK_OP_BRN_OP2(op) MASK_BITS_SHIFT(op, 31, 31) #define MASK_OP_BRN_DISP15(op) MASK_BITS_SHIFT(op, 16, 30) +#define MASK_OP_BRN_DISP15_SEXT(op) MASK_BITS_SHIFT_SEXT(op, 16, 30) #define MASK_OP_BRN_N(op) (MASK_BITS_SHIFT(op, 12, 15) + \ (MASK_BITS_SHIFT(op, 7, 7) << 4)) #define MASK_OP_BRN_S1(op) MASK_BITS_SHIFT(op, 8, 11) -- 2.1.2